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ram: generate_regfile, a register file as placed standard cells - #11669

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oharboe:ram-regfile-generator

Closed

ram: generate_regfile, a register file as placed standard cells#11669
oharboe wants to merge 8 commits into
The-OpenROAD-Project:masterfrom
oharboe:ram-regfile-generator

Commits on Oct 8, 2026
- ram: generate_regfile, a multi-port register file as placed standard cells
  
  oharboe
  and
  claude
  committed
  2e98135
- ram: generate_regfile async_reset, a register file that resets to zero
  
  oharboe
  and
  claude
  committed
  f651743
- ram: generate_regfile port check reads SystemVerilog headers, unused ports
  
  oharboe
  and
  claude
  committed
  ec318b0
- ram: generate_regfile write_priority, the later write port wins
  
  oharboe
  and
  claude
  committed
  96dd5ba
- ram: generate_regfile, name Port fields when reading the spec
  
  oharboe
  and
  claude
  committed
  16d446a
- ram: generate_regfile, initialize every Port field by name
  
  oharboe
  and
  claude
  committed
  5975b4e
Commits on Oct 9, 2026
- ram: generate_regfile says what mode netlist leaves unplaced, and tests it
  oharboe
  committed
  8b56108
- ram: generate_regfile, unplaced-periphery info is RAM-0052
  oharboe
  committed
  691d8e1