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asap7/tinyRocket, ORFS's AUTO_MEMORIES design, had not canonicalized: the Rocket Chip generator leaves its cache memories as black boxes (data_arrays_0_ext, data_arrays_0_0_ext, tag_array_ext), the generic sources define none, and AUTO_MEMORIES only detects a memory yosys infers. Only tag_array, forced by an override, got a macro; data_arrays_0_ext was "not part of the design". Under slang the memory extraction stopped earlier on the same unknown modules. Nothing built the design, in ORFS CI (nangate45's tinyRocket maps the memories by hand) or here (auto_memories_outputs_test only analyses it). ORFS patch 0092 adds behavioral models of the three in firtool's read-write convention: the two data arrays become FakeRAM macros, the 4 x 25 tag array flip-flops by the gate's own choice, and its override goes. tinyrocket_synth_build_test builds the synthesis, detection and macro generation included. Floorplan to global route in under three minutes; the flow's minimum period estimate 1243 ps on the 1600 ps clock, 3956 um2 at 41 %. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
…R does The README says what makes asap7/tinyRocket unique among the designs: its cache memories found and made FakeRAM macros by AUTO_MEMORIES rather than mapped by hand, its integer register file and SRAMs both identified by yosys in one inventory, and minutes from synthesis to global route. Checked on yosys's own frontend, ORFS's default: two macros, the inventory as the README lists it. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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asap7/tinyRocket, ORFS's AUTO_MEMORIES design, builds again. It now serves as the fast-turnaround case for register files built through yosys's memlib + techmap, which come next and separately.Why it was broken, and why nobody saw it
The Rocket Chip generator leaves its cache memories as black boxes:
data_arrays_0_ext,data_arrays_0_0_extandtag_array_ext. The generic tinyRocket sources define none of them.$mem_v2. Onlytag_arraygot a macro, because a.memoriesoverride forced it. The two data arrays went undetected, and canonicalization stopped:Nothing built the design:
auto_memories_outputs_testanalyses tinyRocket's synthesis without running it.The fix
ORFS patch 0092, carried and not upstreamed:
designs/asap7/tinyRocket/memories.vhas behavioural models of the three memories in firtool's read-write convention, with the read address registered as firtool writes it. yosys then infers each one as a clocked-read memory, and AUTO_MEMORIES decides:data_arrays_0_extdata_arrays_0_0_exttag_array_extRocket._T_288, the integer register filetag_array.memoriesis deleted. With a behavioural model, the gate's own choice stands. The docs' override example no longer names it.schema_test's tag_array case, whose fixture it was, goes too;test_merge_new_entry_taken_wholestill covers an override taken whole.Patch 0092 skips 0089–0091, which #1187 uses.
In bazel-orfs
//test:tinyrocket_synth_build_testbuilds the synthesis, AUTO_MEMORIES detection and macro generation included. It is not manual, so CI runs it.Tested
//test:tinyrocket_synth_build_test,//test:auto_memories_outputs_test,//test:no_auto_memories_outputs_testschema_test.pyfix_lint,public_surface,host_tools🤖 Generated with Claude Code