ideas: entry 48, AUTO_MEMORIES_REGFILES on XSTile, the parent +224 ps

[oharboe]

Records the first XiangShan run of #1187 in the lab log, to revisit. No fix in this PR.

What was measured: #1187 at aeae86ac, with main at 4b67304b merged in, XSTile built from source to global route, against KPI row 12.

part	row 12	#1187 aeae86ac
parent, the design's period	3,162 ps	3,386 ps
Frontend	2,170 ps	2,170 ps
MemBlock	1,870 ps	1,870 ps
CoupledL2	1,572 ps	1,572 ps
VecRegionModule	1,479 ps	1,479 ps
FltRegionModule	895 ps	895 ps

What is known:

• Every block is identical to row 12.
• The parent is 7.1 % slower, on row 12's own worst path, which is CtrlBlock logic. That is not the pattern of structured_gen: the register file's periphery is the parent's #1184 (+21.9 %, entry 47), which AUTO_MEMORIES_REGFILES: register files as macros that dissolve after macro placement #1187 includes: all of structured_gen: the register file's periphery is the parent's #1184's worst paths ended at Frontend's inputs.

What is open: where the parent's +224 ps comes from. The entry names the measurement that would answer it: entry 47's zero-wire census on this run's global-route checkpoint, preferably on #1187's current tip, which has changed the dissolve since.

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