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study-pr: a period is a clock's, and a seed is noise - #1194
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Two lessons from the register-file campaign on ORFS's asap7 designs: - ORFS's timing__fmax is the largest fmax over all clocks, virtual I/O clocks included, so with a vclk_<name> in the SDC it can be the I/O clock's (ibex: 807 ps against 970 ps for core_clock; OpenROAD#11668). Read the design clock's own metric, or the reg2reg group's clk_period - WNS. find_clk_min_period's argument is include_port_paths. - A placement seed is part of the noise: picorv32's A/B read +4.0, +3.4 and -3.3 % at three seeds; one seed per arm resolves nothing smaller. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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Two noise-discipline lessons for
study-pr, from the register-file campaign (#1187):timing__fmaxis the largest fmax over all clocks, virtual I/O clocks included: ibex's read 807 ps against 970 ps forcore_clock(timing__fmax includes virtual clocks since ORFS added virtual I/O clocks. Intended? OpenROAD#11668). Readtiming__fmax__clock:<design clock>, or thereg2reggroup'sclk_period - WNS.GPL_RANDOM_SEED1, 2 and 3; one seed per arm resolves nothing smaller.🤖 Generated with Claude Code