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test/regfile/cores: generate_regfile's reset, SV ports and write priority under test - #1210
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…rity under test OpenROAD patch 0010 (OpenROAD#11669) has spec keys nothing on main exercised: async_reset, the port check reading a SystemVerilog header, `unused` inputs and `write_priority last`. OpenROAD's own tests for them do not run from bazel-orfs. Each is now simulated against the RTL it replaces, every read compared under random reads, writes and resets, seconds per test: - ibex_sim_test: ibex's register file, ORFS's src/ibex_sv RTL as it is, with its async reset (29 resets in 20,000 cycles), a parameterised SystemVerilog header and two unused inputs. ibex_no_reset_sim_test, the spec without the reset, must mismatch. - write_last_sim_test: an 8 x 8 file with two write ports that collide, the later port winning. write_first_sim_test, RTL where the earlier port wins, must mismatch, or the stimulus never collides. The harness (sim.bzl, gen_tb.py, tb_main.cc) is the register-file ladder's from the closed #1187, without its surgery comparison. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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OpenROAD patch 0010 (OpenROAD#11669) carries generate_regfile spec keys that nothing on main exercised:
async_reset, the port check reading a SystemVerilog header,unusedinputs andwrite_priority last. OpenROAD's own tests for them do not run from bazel-orfs. This simulates each against the RTL it replaces, every read compared under random reads, writes and resets, in well under a second per test:ibex_sim_testsrc/ibex_svRTL unchanged: async reset, parameterised SV header, two unused inputsibex_no_reset_sim_testwrite_last_sim_testwrite_first_sim_testNo ORFS patch is needed: the ibex spec lives in the test package. The harness (
sim.bzl,gen_tb.py,tb_main.cc) is the register-file ladder's from the closed #1187, without its surgery comparison. It is simulation with Verilator, not LEC, so it does not depend on kepler-formal.🤖 Generated with Claude Code