A Extension, Reservation Table, and Multi-threading Support

[giancarlopernudisegura]

This PR seeks to solve #75. To implement the A extension and use it to its fullest extent, we also need to implement a reservation table tool and some multi-threading support. Since this is a lot of work and we're not even done, I'm creating this draft PR to keep track and get early feedback since we're not even done and the changes are already huge.

Our current progress

So far we've implemented:

• All the instructions in the specification for the A extension. We don't have any support for the aq and rl bits and don't plan on supporting it unless there's a good reason for it. Both 32-bit and 64-bit instructions are implemented.
• Reservation Table and accompanying tool. The underlying structure of a Reservation table needed for the lr/sc instructions is implemented, any address reserved that gets overwritten (in 32-bit mode) will be unreserved. The table allows the user to manually unreserve reserved addresses (reserved with the lr.w and lr.d instructions) in order to simulate another hart writing to memory which will make sc.w and sc.d fail as otherwise, it would always succeed since there currently aren't any other harts.
• Atomic Instructions get properly categorized in the instruction statistics tool. This was done thanks to Port InstructionStatistics getInstructionCategory function to RISCV #120.

TODO

• There are some edge cases when unreserving addresses in 64-bit mode that we're going to fix.
• We have to write unit tests for all the instructions that we're adding
• We need to add multi-threading. Right now, we have added a harts variable to know how many threads to run the RISC-V program with but it's hardcoded to 0. We're taking the route suggested in Support A extension #75 by making multi-threading a tool. We expect this to be the hardest part out of everything.