QOI_FPGA_Accelerator

An FPGA-based implementation of a QOI image compression hardware accelerator.

Contents

• FPGA

  • This directory contains SystemVerilog for the design and testbench
  • The hardware used for this implementation is the UPduino v3.1 with the iCE40 UP5K FPGA. The usable bitmap file can be found at FPGA/impl_1/QOI_Ram_impl_1.bin, and the source files can be found in FPGA/source/impl_1

• MCU

  • To send and recieve an image to the FPGA, we use the STM32L432KC ARM Cortex-M4 MCU
  • The MCU sends an image over SPI to the FPGA, and then pings the FPGA for a ready signal, which indicated when the FPGA is done compressing the image. After it is, the FPGA sends the image back to the MCU over spi

This project was written as a part of the larger NeoObscura project, a from-scratch camera sensor built from 1200 phototransistors.