VUnit · eine · Jun 4, 2019 · Jun 4, 2019 · Jun 4, 2019 · Jun 11, 2019
diff --git a/docs/verification_components/user_guide.rst b/docs/verification_components/user_guide.rst
@@ -107,6 +107,4 @@ and the VC-developers.
    :maxdepth: 1
    :hidden:
 
-   vci/bus_master
-   vci/stream
-   vci/sync
+   vci/vci
diff --git a/docs/verification_components/vci/bus_master.rst b/docs/verification_components/vci/bus_master.rst
diff --git a/docs/verification_components/vci/stream.rst b/docs/verification_components/vci/stream.rst
diff --git a/docs/verification_components/vci/sync.rst b/docs/verification_components/vci/sync.rst
diff --git a/docs/verification_components/vci/vci.rst b/docs/verification_components/vci/vci.rst
@@ -0,0 +1,37 @@
+.. _bus_master_vci:
+
+Bus Master VCI
+==============
+
+.. literalinclude:: ../../../vunit/vhdl/verification_components/src/bus_master_pkg.vhd
+   :caption: Bus master verification component interface
+   :language: vhdl
+   :lines: 7-
+
+.. _stream_vci:
+
+Stream Master VCI
+=================
+
+.. literalinclude:: ../../../vunit/vhdl/verification_components/src/stream_master_pkg.vhd
+   :caption: Stream master verification component interface
+   :language: vhdl
+   :lines: 7-
+
+Stream Slave VCI
+================
+
+.. literalinclude:: ../../../vunit/vhdl/verification_components/src/stream_slave_pkg.vhd
+   :caption: Stream slave verification component interface
+   :language: vhdl
+   :lines: 7-
+
+.. _sync_vci:
+
+Synchronization VCI
+===================
+
+.. literalinclude:: ../../../vunit/vhdl/verification_components/src/sync_pkg.vhd
+   :caption: Synchronization verification component interface
+   :language: vhdl
+   :lines: 7-
diff --git a/examples/vhdl/array_axis_vcs/run.py b/examples/vhdl/array_axis_vcs/run.py
diff --git a/examples/vhdl/array_axis_vcs/runall_addwave.do b/examples/vhdl/array_axis_vcs/runall_addwave.do
diff --git a/examples/vhdl/array_axis_vcs/src/axis_buffer.vhd b/examples/vhdl/array_axis_vcs/src/axis_buffer.vhd
diff --git a/examples/vhdl/array_axis_vcs/src/fifo.vhd b/examples/vhdl/array_axis_vcs/src/fifo.vhd
diff --git a/examples/vhdl/array_axis_vcs/src/test/data/in.csv b/examples/vhdl/array_axis_vcs/src/test/data/in.csv