• 🔭 Dissertation: Building a real-time FPGA image processing accelerator (Canny-style pipeline) using HLS C++ on Intel Cyclone V — achieving II = 1, 100 Mpixels/s throughput, and timing closure at Fmax ≥ 138.87 MHz
• 🎓 MSc Telecommunications & Wireless Systems at University of Liverpool — Distinction predicted
• ⚡ B.Tech highlight: Designed energy-efficient approximate multipliers in Verilog (Cadence Genus, 90 nm CMOS) — 96.9% power reduction and 95.5% area reduction vs. standard array multipliers
• 🛠️ Proficient in Verilog, VHDL, SystemVerilog, HLS C++ (Intel i++), with hands-on EDA experience across Quartus Prime, Platform Designer (Qsys), QuestaSim, and Cadence Genus/Tempus
• 📫 Reach me at varunvenkatatej7@gmail.com | Open to UK graduate FPGA, VLSI, and Digital Design roles

HDL & Hardware Description

EDA & Design Tools

Programming & Scripting

ML & Data

Full Canny-style edge detection pipeline (Gaussian blur → Sobel → NMS → double-threshold) implemented as a single HLS C++ kernel on Intel Cyclone V with Avalon-ST interfaces and live VGA output.

• Result: II = 1 | 100 Mpixels/s (~325 fps @ 640×480) | Fmax ≥ 138.87 MHz | 7,398 ALMs (23%)
• Tools: Intel HLS Compiler (i++), Quartus Prime 18.1, Platform Designer (Qsys), DE1-SoC, SDC constraints

Designed novel Type-1 and Type-2 approximate compressors in Verilog to eliminate carry-chain logic; validated output quality using PSNR/SSIM on an image sharpening pipeline.

• Result: 96.9% power reduction | 95.5% area reduction | 92.3% delay reduction (vs. standard 8-bit multiplier)
• Tools: Verilog, QuestaSim 10.6c, Cadence Genus (90 nm CMOS), Cadence Tempus, MATLAB

Vision-based real-time sign language classifier — trained and benchmarked Random Forest, SVM, and KNN on 747-sample hand landmark data; deployed live via OpenCV camera pipeline.

• Result: Random Forest selected as primary classifier based on F1 score and noise robustness
• Tools: Python, scikit-learn, OpenCV, pandas, NumPy

_{Open to UK graduate roles in FPGA Design · VLSI · Digital Hardware · Semiconductor Engineering}