Skip to content

Fixing the evaluating of HLS metadata for simulation#74

Merged
hpc-aulmamei merged 2 commits into
Xilinx:devfrom
JOOpdenhoevel:fix/sim_hls_metadata
May 6, 2026
Merged

Fixing the evaluating of HLS metadata for simulation#74
hpc-aulmamei merged 2 commits into
Xilinx:devfrom
JOOpdenhoevel:fix/sim_hls_metadata

Conversation

@JOOpdenhoevel
Copy link
Copy Markdown
Collaborator

generate_sim_tcl was overwriting its kernel_hls_by_type mapping with an empty dict immediately after building it, so build_system_map_context received no HLS metadata and silently fell back to the register-stem heuristic in _build_functional_args_fallback.

The user-visible effect: for simulation builds, buffer-typed <arg> entries in system_map.xml were emitted without the port= attribute (the fallback has no access to the hwRefs interface info needed to resolve the AXI4FULL port), and arg name attributes were derived from register stems rather than the original HLS argument name. Emulation builds were unaffected because generate_emu_tcl populates the dict correctly.

Reproduction

Build examples/00_axilite for both emulation and simulation and diff the two system_map.xml files. Before this fix, the increment_0 buffer arg appears as:

<!-- emu (correct) -->
<arg idx="1" name="in_r" type="buffer" offset="0x18" range="64" r="0" w="1" port="m_axi_gmem0" />

<!-- sim (broken) -->
<arg idx="1" name="input_r" type="buffer" offset="0x18" range="64" r="0" w="1" />

Fix

Drop the stray kernel_hls_by_type: dict[str, Path] = {} re-declaration in linker/v80pp/emit/sim/tcl_gen.py so the populated mapping survives into build_system_map_context. With HLS metadata available, the existing logic at system_map_ctx.py:249-271 correctly resolves and emits the port= attribute, and arg names come from the HLS Args rather than register stems.

Signed-off-by: Jan-Oliver Opdenhövel <Jan-Oliver.Opdenhovel@amd.com>
@quetric quetric requested a review from hpc-aulmamei May 5, 2026 09:16
Signed-off-by: Jan-Oliver Opdenhövel <Jan-Oliver.Opdenhovel@amd.com>
@JOOpdenhoevel
Copy link
Copy Markdown
Collaborator Author

The issue with the VRT unit tests was that they would run a system update before installing new packages. Apparently, this sometimes brakes and isn't best practice, so I have removed the system update. Now, it works and should also work for all other PRs with failing VRT unit testing workflows.

@hpc-aulmamei
Copy link
Copy Markdown
Collaborator

lgtm

@hpc-aulmamei hpc-aulmamei merged commit 8c08d83 into Xilinx:dev May 6, 2026
2 checks passed
@JOOpdenhoevel JOOpdenhoevel deleted the fix/sim_hls_metadata branch May 6, 2026 09:55
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

2 participants