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Signed-off-by: Marcel Flottmann <github@lecramdev.de>
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For larger networks, the time of the blockdesign generation increases significantly, because Vivado reparses all verilog files for every added block/module.
The RTL code is packed as an additional step in
code_generation_ipgenaftergenerate_hdl. ThePrepareIPtransformation would take longer, therefore, it is now derived fromNodeLocalTransformationto process all nodes in parallel.