Add synthesizable pulse_gen Vivado deliverables (RTL, self-checking TB, constraints, and sim flow)

[Copilot]

This PR adds a complete Artix-7-targeted Vivado deliverable set for a parameterized SystemVerilog pulse generator (pulse_gen) using 100 MHz timing assumptions (10 ns units). It includes RTL, self-verifying simulation collateral, constraints, and concise build/timing guidance.

• RTL: pulse_gen implementation

  • Added rtl/pulse_gen.sv with parameterized counters (WIDTH_BITS=8, PERIOD_BITS=16).
  • Implements interval pulse generation with:
    • pulse high for width cycles per period cycle window
    • busy asserted while actively generating
    • reset/disable/zero-parameter handling that clears state
  • Width is clamped to period for safe behavior when width >= period.

• Verification: self-checking testbench

  • Added sim/tb_pulse_gen.sv with automated checks for:
    • reset behavior
    • minimum width/period case
    • maximum width/period case
    • enable deassert/reassert behavior
  • Testbench validates both pulse duty/period pattern and busy status over long-cycle scenarios.

• Vivado collateral

  • Added constraints/pulse_gen.xdc with 100 MHz clock constraint (create_clock -period 10.000 on clk).
  • Added scripts/sim.do supporting both Questa (vlog/vsim) and Vivado simulator (xvlog/xelab/xsim) invocation paths.
  • Updated README.md with concise simulation/project/implementation/timing-report instructions (including Fmax > 100 MHz expectation from timing summary).
  • Added sim/results.txt with expected waveform behavior summary from a mental run.

module pulse_gen #(
    parameter int WIDTH_BITS  = 8,
    parameter int PERIOD_BITS = 16
) (
    input  logic                   clk, rst_n, enable,
    input  logic [WIDTH_BITS-1:0]  width,
    input  logic [PERIOD_BITS-1:0] period,
    output logic                   pulse, busy
);

Original prompt

TASK: Build a complete Vivado project for a Verilog pulse generator module.

FUNCTIONAL SPEC:

• Module: pulse_gen
• Inputs: clk (100MHz), rst_n, enable, width[7:0], period[15:0]
• Outputs: pulse, busy
• Behavior: When enabled, generate pulse at period interval. Pulse width = width * 10ns. Period = period * 10ns.

DELIVERABLES (create these files):

1. rtl/pulse_gen.sv
2. sim/tb_pulse_gen.sv
3. constraints/pulse_gen.xdc (100MHz clock)
4. scripts/sim.do (Questa/Vivado sim script)
5. README.md (brief build instructions, 5 bullets max)

REQUIREMENTS:

• Synthesizable for Xilinx Artix-7 (XC7A100T)
• Use parameterized counters (WIDTH_BITS=8, PERIOD_BITS=16)
• Testbench must self-verify: test minimum/maximum width, period, enable toggle, reset behavior
• Generate timing report showing Fmax > 100MHz

AGENT INSTRUCTIONS:

• Write all RTL in SystemVerilog
• Use clean, minimally commented code (comments are fine, but avoid narrative text outside code)
• After writing files, run a quick simulation mentally and describe expected waveform in sim/results.txt
• DO NOT write long explanations. Just generate the files.
• If asked for status, reply with "Files created. Ready for synthesis."

[Copilot]

Pull request overview

Note

Copilot was unable to run its full agentic suite in this review.

Adds a parameterized pulse generator RTL block plus a self-checking simulation testbench and scripts/docs to run simulation and basic Vivado flow.

Changes:

• Added pulse_gen.sv RTL for periodic pulse generation (width/period/enable, busy output).
• Added SystemVerilog testbench tb_pulse_gen.sv and a simulator script scripts/sim.do to run it (Questa or Vivado xsim).
• Added Vivado constraints for clk and expanded README with simulation/implementation commands.

Reviewed changes

Copilot reviewed 6 out of 6 changed files in this pull request and generated 5 comments.

Show a summary per file

File	Description
sim/tb_pulse_gen.sv	New self-checking SV testbench for pulse_gen.
sim/results.txt	Documents expected waveform behavior for key configurations.
scripts/sim.do	Adds a unified script attempting to run in Questa or Vivado xsim.
rtl/pulse_gen.sv	New parameterized pulse generator RTL implementation.
constraints/pulse_gen.xdc	Adds a 100 MHz clock constraint and pin/IO standard for clk.
README.md	Adds instructions for running simulation and Vivado implementation/timing checks.

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