CMOS Amplifier using Cascode Current Sink Biasing

Objective

Design a Cascode Current Sink (Type 3) with a two stage CMOS Op-Amp (Type 1) that delivers a stable $100 uA$ tail current under supply voltage of $1.8 V$

Specifications

Cascode Current Sink

Spec	Value
$V_{DD}$	$1.8V$
$V_{SS}$	$0V$
Tail Current	$100 uA$

CMOS Op-Amp

Spec	Value
Gain-Bandwidth Product	$5 MHz$
Voltage Gain	$1000$
Phase Margin	$> 60^\circ$
Slew Rate	$> 5 V/us$
ICMR (Input common mode range)	$0.8V - 1.6V$
Tail Current	$100 uA$

Final Schematic (sizing)

Final Schematic (current flow)

Circuit used to optimize Op-Amp circuit

AC Gain & Phase Margin Plot

ICMR Plot

Slew Rate

Iterations

Specification	Iteration 1	Iteration 2	Iteration 3	Iteration 4	Percentage Improvement
Input Common Mode Range(V)	1.28 - 1.8	1.2 - 1.8	1.2 - 1.8	1.2 - 1.8	Marginal
Slew Rate(V/μs)	30.46	7.02	7.37	5.009	83%
Gain (dB)	75.33	75.25	74 .88	63.59	15%
Gain-Bandwidth Product(MHz)	29.54	8.26	8.49	5.60	81%
Phase Margin	43.7°	70.32°	70.15°	70.45	37%
Tail Current(μA)	98.96	98.96	104.8	96 - 104.8	1.04%
Capacitance(pF)	3	13	13	19	Not Applicable

Presentation

Project Report

Project Iterations