GitHub - aferr/TMuxModel: A (very) simple model of a time multiplexed memory hierarchy including a shared bus, pipelined cache, and a memory controller. This was used to study the interaction between these resources when the bus and memory controller are both time multiplexed to prevent timing channel attacks. It includes simulated annealing and hill climbing optimizers to explore the design space of time quanta.

Branches Tags

Name		Name	Last commit message	Last commit date
Latest commit History 8 Commits
BusLayer.rb		BusLayer.rb
MemoryController.rb		MemoryController.rb
PipelinedCache.rb		PipelinedCache.rb
State.rb		State.rb
hill_climb.rb		hill_climb.rb
latency_model.rb		latency_model.rb
simulated_annealing.rb		simulated_annealing.rb

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A (very) simple model of a time multiplexed memory hierarchy including a shared bus, pipelined cache, and a memory controller. This was used to study the interaction between these resources when the bus and memory controller are both time multiplexed to prevent timing channel attacks. It includes simulated annealing and hill climbing optimizers …