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1. FPGA-based-RISC-V-Processor-Customizable-for-AI-Applications FPGA-based-RISC-V-Processor-Customizable-for-AI-Applications Public

   FPGA-implemented RISC-V processor, evolved from single-cycle to 5-stage pipelined architecture for higher performance and timing efficiency. BRAM-based instruction memory optimizes FPGA usage. Full…

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2. ML-based-heart-rate-anomaly-detector-for-RISC-V ML-based-heart-rate-anomaly-detector-for-RISC-V Public

   Lightweight, low-power heart-rate anomaly detector for wearable devices. Implements a fixed-point linear regression model on a custom RV32I processor, fully FPGA-compatible with BRAM memory support…

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3. Hardware-Accelerated-Heart-Rate-Anomaly-Detection Hardware-Accelerated-Heart-Rate-Anomaly-Detection Public

   RTL implementation of a RISC-V processor integrated with a custom hardware accelerator for heart-rate anomaly detection. The SoC-style architecture uses memory-mapped I/O to transfer physiological …

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4. K-Nearest-Neighbours-KNN-Classifier-in-Verilog K-Nearest-Neighbours-KNN-Classifier-in-Verilog Public

   Verilog RTL implementation of a K-Nearest Neighbours (KNN) classifier using an FSM-based architecture. Computes squared Euclidean distances, tracks the 7 nearest labelled neighbours, and performs m…

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5. Design-and-Implementation-of-a-Weight-Stationary-Systolic-Array-Based-GEMM-Hardware-Accelerator Design-and-Implementation-of-a-Weight-Stationary-Systolic-Array-Based-GEMM-Hardware-Accelerator Public

   Verilog-based 3x3 weight-stationary systolic array hardware accelerator for 9x9 General Matrix Multiplication using a 3x3 tiling approach. Features a hierarchical RTL design with custom Processing …

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