Interested in FPGA/ASIC design and verification, analog design, EDA and software development
- Egypt
Highlights
- Pro
Pinned Loading
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aes-coprocessor
aes-coprocessor PublicRISC-V scalar cryptography extension coprocessor-based implementation based on the CV-X-IF interface
SystemVerilog 2
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rich-slate
rich-slate PublicOpinionated rich text editor on top of slate (Under development)
TypeScript 5
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