ccg firmware update support for cyacd2 - #2
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Add support for B-frame configuration on both gen1 and gen2 encoders by enabling V4L2_CID_MPEG_VIDEO_B_FRAMES control. Link: https://lore.kernel.org/all/20260512-batch2_features-v7-3-4954e3b4df84@oss.qualcomm.com/ Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-HDK Signed-off-by: Wangao Wang <wangao.wang@oss.qualcomm.com> Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
Add hierarchical coding support for both gen1 and gen2 encoders by enabling the following V4L2 controls: H264: V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING, V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_TYPE, V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER HEVC(gen2 only): V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_TYPE, V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_LAYER Link: https://lore.kernel.org/all/20260512-batch2_features-v7-4-4954e3b4df84@oss.qualcomm.com/ Reviewed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com> Signed-off-by: Wangao Wang <wangao.wang@oss.qualcomm.com> Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
…t_property Modify iris_hfi_gen1_packet_session_set_property to simplify size calculations and remove redundant code patterns. Previously, packet->shdr.hdr.size was incremented by sizeof(u32) in every switch case, resulting in repetitive and less maintainable logic. Link: https://lore.kernel.org/all/20260512-batch2_features-v7-5-4954e3b4df84@oss.qualcomm.com/ Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-HDK Signed-off-by: Wangao Wang <wangao.wang@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
Unify AVC/HEVC handling by computing codec and lcu_size upfront. Link: https://lore.kernel.org/all/20260512-batch2_features-v7-6-4954e3b4df84@oss.qualcomm.com/ Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-HDK Signed-off-by: Wangao Wang <wangao.wang@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
The struct iris_fmt unites pixfmt with the plane type, however the type from the struct is not actually used. Drop the struct completely and use u32 pixfmt in all the callsites. Link: https://lore.kernel.org/all/20260529-iris-remote-fmts-v7-1-a8bd57ac8b5a@oss.qualcomm.com/ Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
Use div_u64() instead of mult_fract as u64 operator division fails on 32 bit systems which don't link against libgcc. Link: https://lore.kernel.org/all/20260602-fixbranch-v1-1-b8eccaad6d17@kernel.org/ Fixes: 5c66647 ("media: iris: add FPS calculation and VPP FW overhead in frequency formula") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202606030132.qnBXVDkM-lkp@intel.com/ Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
To simplify code checking for pixel formats, add helpers to check for 8bit and 10bit formats. Link: https://lore.kernel.org/all/20260602-topic-sm8x50-iris-10bit-decoding-v5-1-c2b32474ed67@linaro.org/ Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Tested-by: Wangao Wang <wangao.wang@oss.qualcomm.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
The P010 (YUV format with 16-bits per pixel with interleaved UV) and QC10C (P010 compressed mode similar to QC08C) requires specific buffer calculations to allocate the right buffer size for the DPB (decoded picture buffer) frames and frames consumed by userspace. Similar to 8bit, the 10bit DPB frames uses QC10C format. Link: https://lore.kernel.org/all/20260602-topic-sm8x50-iris-10bit-decoding-v5-2-c2b32474ed67@linaro.org/ Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Tested-by: Wangao Wang <wangao.wang@oss.qualcomm.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
Add the necessary plumbing into the HFi Gen2 to signal the decoder the right 10bit pixel format and stride when in compressed mode. Link: https://lore.kernel.org/all/20260602-topic-sm8x50-iris-10bit-decoding-v5-3-c2b32474ed67@linaro.org/ Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Tested-by: Wangao Wang <wangao.wang@oss.qualcomm.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
…s for 10bit formats Update the gen2 response and vdec s_fmt code to take in account the P010 and QC010 when calculating the width, height and stride. Link: https://lore.kernel.org/all/20260602-topic-sm8x50-iris-10bit-decoding-v5-4-c2b32474ed67@linaro.org/ Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Tested-by: Wangao Wang <wangao.wang@oss.qualcomm.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
…and 10bit formats The 10bit pixel format can be only used when the decoder identifies the stream as decoding into 10bit pixel format buffers, so update the find_format helper to filter the formats and only allow the proper formats when setting or trying a capture format. Link: https://lore.kernel.org/all/20260602-topic-sm8x50-iris-10bit-decoding-v5-5-c2b32474ed67@linaro.org/ Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Tested-by: Wangao Wang <wangao.wang@oss.qualcomm.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
Add the necessary bits into the gen2 platforms tables and handlers to allow decoding streams into 10bit pixel formats. Link: https://lore.kernel.org/all/20260602-topic-sm8x50-iris-10bit-decoding-v5-6-c2b32474ed67@linaro.org/ Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Tested-by: Wangao Wang <wangao.wang@oss.qualcomm.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
…50lt encoder Add Long-Term Reference(LTR) frame support for ar50lt gen2 encoder by enabling the following V4L2 controls: V4L2_CID_MPEG_VIDEO_LTR_COUNT V4L2_CID_MPEG_VIDEO_USE_LTR_FRAMES V4L2_CID_MPEG_VIDEO_FRAME_LTR_INDEX The ar50lt gen2 firmware supports the corresponding LTR HFI properties. Link: https://lore.kernel.org/all/20260710-shikra_ltr_support-v1-1-458b587268ea@oss.qualcomm.com/ Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com> Signed-off-by: Gourav Kumar <gouravk@qti.qualcomm.com>
…oder Add LAYER_ENABLE, LAYER_TYPE_H264/HEVC, LAYER_COUNT_H264/HEVC and per-layer bitrate fw_caps entries to inst_fw_cap_gen2_ar50lt_enc, enabling V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING and related hierarchical/layered encoding controls for ar50lt platforms. Link: https://lore.kernel.org/all/20260710-shikra_ltr_support-v1-2-458b587268ea@oss.qualcomm.com/ Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com> Signed-off-by: Gourav Kumar <gouravk@qti.qualcomm.com>
When validating a capture format, check_format() compares the requested pixel format against inst->fw_caps[BIT_DEPTH]. However, the bit depth capability is not available at this stage and it contains the default value of BIT_DEPTH_8. The actual bit depth is updated later after the firmware reports stream capabilities through read_input_subcr_params(). Because of this, a valid client request of QC10C format request is rejected during the initial format negotiation. The driver then falls back to the default capture format (NV12) and stores it as capture format. Later, when the firmware reports that the stream is 10-bit, the driver sees NV12 as the selected capture format and switches to the default 10-bit format (P010). As a result, the original QC10C format requested by userspace is lost and QC10C decoding cannot work correctly. The bit depth information is not reliable during the initial format setup, so it should not be used to validate capture formats. Remove the bit-depth checks from check_format() and only verify that the requested pixel format is supported. This allows the format requested by userspace is handled correctly. Link: https://lore.kernel.org/all/20260710-qc10c_fix_and_disable_time_delta_based_rc-v2-1-701d6dfd1ac1@oss.qualcomm.com/ Fixes: 20c3ef4 ("media: qcom: iris: vdec: update find_format to handle 8bit and 10bit formats") Cc: stable@vger.kernel.org Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com> Reviewed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
The iris encoder driver was not sending HFI_PROP_TIME_DELTA_BASED_RATE_CONTROL to the firmware during encoder initialization. Without this property, the firmware defaults to time-delta-based rate control (enabled), which calculates the output bitrate from actual frame timing rather than following the configured bitrate target. This caused variable bitrate (VBR) encoding to produce ~5x configured bitrate. For example, with video_bitrate=896000 (896 Kbps), the output is ~4.4 Mbps instead of the expected ~896 Kbps. Time-delta-based rate control is designed for variable frame rate (VFR) scenarios where the encoder adapts to actual frame timing. However, when an application explicitly configures a bitrate target, the firmware must follow that target regardless of frame timing. Fix this by adding the TIME_DELTA_BASED_RC capability with a default value of 0 (disabled) and sending HFI_PROP_TIME_DELTA_BASED_RATE_CONTROL = 0 to the firmware during stream-on, allowing the firmware to use the configured bitrate as the target. Link: https://lore.kernel.org/all/20260710-qc10c_fix_and_disable_time_delta_based_rc-v2-2-701d6dfd1ac1@oss.qualcomm.com/ Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com> Reviewed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com> Signed-off-by: Gourav Kumar <gouravk@qti.qualcomm.com>
…' into shikra-debug
During recovery, it is not safe to retire the hung submit before we recover the GPU. Retiring the submit triggers BO free and that can result in GPU pagefaults since the GPU may be actively accessing those BOs. To fix this, retire the submits after gpu recovery is complete in recover_worker(). Fixes: 1a370be ("drm/msm: restart queued submits after hang") Signed-off-by: Veeresh Bagale <vbagale@qti.qualcomm.com> Signed-off-by: Jie Zhang <jie.zhang@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Link: https://lore.kernel.org/linux-arm-msm/20260605-assorted-fixes-june-v1-2-2caa04f7287c@oss.qualcomm.com
The GPUCC register list for A663 is incorrect, which can cause out-of-bounds register access during GPU state capture. Update it to use the correct register ranges. Fixes: 5773cce ("drm/msm/a6xx: Add support for A663") Signed-off-by: Veeresh Bagale <vbagale@qti.qualcomm.com> Signed-off-by: Jie Zhang <jie.zhang@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Link: https://lore.kernel.org/linux-arm-msm/20260605-assorted-fixes-june-v1-3-2caa04f7287c@oss.qualcomm.com
A621 uses an incorrect GPUCC register list during state capture. The existing list matches A623/A663. Rename it accordingly and add a dedicated A621 GPUCC register list. Fixes: 11cdb81 ("drm/msm/a6xx: Fix gpucc register block for A621") Signed-off-by: Veeresh Bagale <vbagale@qti.qualcomm.com> Signed-off-by: Jie Zhang <jie.zhang@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Link: https://lore.kernel.org/linux-arm-msm/20260605-assorted-fixes-june-v1-4-2caa04f7287c@oss.qualcomm.com
Once a hang is triggered by the msm_recovery test, the gpu error irq remains asserted and triggers an interrupt storm. In the worst case, this IRQ storm lands on the CPU core where the hangcheck timer is scheduled, blocking it from running. This eventually leads to CPU watchdog timeouts. To fix this, mask the gpu error irqs during msm_recovery test and enable them back during the recovery. Fixes: 5edf275 ("drm/msm: Add debugfs to disable hw err handling") Signed-off-by: Veeresh Bagale <vbagale@qti.qualcomm.com> Signed-off-by: Jie Zhang <jie.zhang@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Link: https://lore.kernel.org/linux-arm-msm/20260605-assorted-fixes-june-v1-5-2caa04f7287c@oss.qualcomm.com
get_pid_task() increments the task reference count, but the corresponding put_task_struct() was missing in the else branch, leaking a reference on every GPU hang recovery. Fixes: 25654a1 ("drm/msm: Update global fault counter when faulty process has already ended") Signed-off-by: Veeresh Bagale <vbagale@qti.qualcomm.com> Signed-off-by: Jie Zhang <jie.zhang@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Link: https://lore.kernel.org/linux-arm-msm/20260605-assorted-fixes-june-v1-6-2caa04f7287c@oss.qualcomm.com Signed-off-by: Veeresh Bagale <vbagale@hu-vbagale-hyd.qualcomm.com>
…ase firmware table Add purwa-iot-evk and qcs6490-rb3gen2 platform support to the usecase firmware lookup table for WCN6855 hw2.1. These platforms use the nfa765 firmware path for usecase-based firmware selection. Also reorder the table entries by compatible string. Tested-on: WCN6855 hw2.1 PCI WLAN.HSP.1.1-04685-QCAHSPSWPL_V1_V2_SILICONZ_IOE-1 Signed-off-by: Miaoqing Pan <miaoqing.pan@oss.qualcomm.com> Link: https://lore.kernel.org/linux-wireless/20260713020359.3618193-1-miaoqing.pan@oss.qualcomm.com/
…upply routing Align with latest upstream submission by adding the wcn3988-pmu node, routing bluetooth/wifi supplies through PMU child regulators, adding sw_ctrl pinctrl and bluetooth compatible to the shared dtsi, and fixing the wifi firmware-name to "shikra" across all EVK variants. Link: https://lore.kernel.org/all/20260608-shikra-dt-m1-v4-10-2114300594a6@oss.qualcomm.com/ Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Commit is NAKed in upstream, so reverting for now. This reverts commit 2f074ad. Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>
…e paths" Commit is NAKed in upstream, so reverting for now. This reverts commit 1a9b2e0. Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>
Commit is NAKed in upstream, so reverting for now. This reverts commit ec012bf. Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>
…ount" Commit is NAKed in upstream, so reverting for now. This reverts commit e4d89a3. Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>
Commit is NAKed in upstream, so reverting for now. This reverts commit f28f9a0. Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>
…on read failure" Commit is NAKed in upstream, so reverting for now. This reverts commit 87dab5e. Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>
PCI: Add support for PCIe WAKE# interrupt
Mahua shares the same QREF TX/RPT/RX component naming as Glymur, but has a different topology: a single QREF block fed by REFGEN4 only, rather than the two independent blocks fed by REFGEN3 and REFGEN4 on Glymur. Add qcom,mahua-tcsr compatible and document its required supply properties. Note that REFGEN4 is supplied by regulators vdda-refgen3-1p2 and vdda-refgen3-0p9 on Mahua. Link: https://lore.kernel.org/all/20260702-tcsr_qref_0702-v7-0-776f2811b7af@oss.qualcomm.com/ Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
…PHY on Glymur The PCIe PHYs on Glymur require a reference voltage provided by REFGEN, which in turn is powered by two LDOs. Since there is no devicetree node for REFGEN, add the vdda-refgen0p9 and vdda-refgen1p2 supplies for each PCIe PHY node. Link: https://lore.kernel.org/all/20260623-phy_refgen-v2-0-4d15983bf91d@oss.qualcomm.com/ Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
The TCSR clkref_en clocks gate the QREF block which provides reference clocks to the PCIe PHYs. Wire up the LDO supplies required by the QREF and refgen blocks on the CRD board. Link: https://lore.kernel.org/all/20260702-tcsr_qref_0702-v7-0-776f2811b7af@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Wire up the LDO supplies required by the QREF and refgen blocks on Purwa and Hamoa boards. Purwa's QREF topology is same as Hamoa's, so it reuses the same qcom,x1e80100-tcsr compatible and supply set rather than needing a dedicated one. Link: https://lore.kernel.org/linux-arm-msm/20260714-hamoa_tcsr_qref_0714_2-v1-3-13047922a376@oss.qualcomm.com/ Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
… for Glymur The PCIe QMP PHYs require a stable reference voltage provided by REFGEN, which in turn requires two separate LDOs to operate. Add vdda-refgen0p9-supply and vdda-refgen1p2-supply properties. Mark them as required for the Glymur PCIe QMP PHYs for now; other platforms having the same requirement and can be added later. Link: https://lore.kernel.org/all/20260623-phy_refgen-v2-1-4d15983bf91d@oss.qualcomm.com/ Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
The refgen providing reference voltage for PCIe QMP PHY on Glymur requires two power supplies independent from the PHY's core and qref rails. Add support for vdda-refgen0p9 and vdda-refgen1p2 supplies with a dedicated glymur_qmp_phy_vreg_l list. Update both Gen5x4 and Gen4x2 configurations to use the new supply list. Link: https://lore.kernel.org/all/20260623-phy_refgen-v2-2-4d15983bf91d@oss.qualcomm.com/ Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
…x#843) Bluetooth: qca: enable QCC2072 on RB3 Gen 2 Industrial
Lt9611uxd DSI HDMI Bridge for Shikra IQS
Add reboot-mode for lemans and monaco
arm64: configs: qcom: reduce SWIOTLB size to 2 MiB
CAMSS: CPHY Support for RB3G2, RB4, RB8
…ks (qualcomm-linux#911) clk: qcom: gcc-shikra: Add additional frequencies for EMAC RGMII clocks
drm/msm: GPU recovery, IRQ, and state capture fixes
…nux#955) wifi: ath12k: fix MLO 4-way handshake timeout on QCC2072
…re table qualcomm-linux#821 wifi: ath11k: add purwa-iot-evk and qcs6490-rb3gen2 to usecase firmware table
…ualcomm-linux#900) media: iris: Fix DMA coherency and frame interval enumeration issues
Output debug information from RSC
…#869) Vote qref in tcsr driver for glymur/mahua/hamoa/purwa
Enable ICE for UFS on Hamoa IoT EVK
…comm-linux#635) arm64: dts: qcom: lemans: Add OPP-table for ICE UFS device node
This reverts commit 1c76289. This out-of-tree USB DT change for the IQS platform is being superseded by the upstream-accepted lore.kernel.org USB series for Shikra, which reintroduces the usb_1/usb_qmpphy nodes with equivalent supply wiring on shikra-iqs-evk in an upstream-aligned form. Revert it here so the upstream series can be applied cleanly on top without duplicate/conflicting nodes. Signed-off-by: Akash Kumar <akash.kumar@oss.qualcomm.com>
This reverts commit 90ffd3d. This out-of-tree USB DT change for the Shikra CQM/CQS platforms is being superseded by the upstream-accepted lore.kernel.org USB series, which reintroduces the usb_1_hsphy/usb_qmpphy nodes and PM4125 supply wiring in an upstream-aligned form. Revert it here so the upstream series can be applied cleanly on top without duplicate/conflicting nodes. Signed-off-by: Akash Kumar <akash.kumar@oss.qualcomm.com>
…o shikra" This reverts the pm4125_hs_in/pm4125_ss_in typec role-switch wiring introduced by commit 102ec26: - Remove the &pm4125_typec connector node and &pm4125_vbus regulator node (with the pm4125_hs_in/pm4125_ss_in endpoint labels) from shikra-cqm-som.dtsi. - Remove the &pm4125_hs_in/&pm4125_ss_in remote-endpoint stanzas and the &usb_1_dwc3_hs/&usb_qmpphy_out remote-endpoint stanzas from shikra-cqm-evk.dts and shikra-cqs-evk.dts. - Restore usb_1's dr_mode to "peripheral" in both files. The &wifi node and all other content are left untouched. Signed-off-by: Akash Kumar <akash.kumar@oss.qualcomm.com>
Add support for both USB controllers and their respective phys on Shikra. Link: https://lore.kernel.org/all/20260811-usb-shikra-v7-v7-0-753e928f37ae@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Signed-off-by: Akash Kumar <akash.kumar@oss.qualcomm.com>
On Shikra CQS/CQM platforms, usb-role-switch is handled by PM4125 on primary Type-C port and Cypress PD controller CYPD6129 on second Type-C port. On Shikra IQS platform, usb-role-switch is handled by Cypress PD controller CYPD6129 on both Type-C ports. Since those changes are not yet present, enabling both USB controllers in device mode. Link: https://lore.kernel.org/all/20260811-usb-shikra-v7-v7-0-753e928f37ae@oss.qualcomm.com/ Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Akash Kumar <akash.kumar@oss.qualcomm.com>
…roller Add the device-tree binding documentation for the Cypress cypd6129 and cypd6229 dual Type-C PD controllers. These are used on Shikra CQM/CQS/IQS platforms to handle usb-role-switch for the USB Type-C ports over an I2C interface, similarly to the existing cypd4226 binding. cypd6229 is a variant of cypd6129 and is described with a "cypress,cypd6129" fallback compatible string. Link: https://lore.kernel.org/all/20260820145036.2035641-4-akash.kumar@oss.qualcomm.com/ Signed-off-by: Akash Kumar <akash.kumar@oss.qualcomm.com>
Add cypd6129 and cypd6229 compatible strings to the of_device_id match table so the driver binds to boards describing these Cypress PD controllers in their device tree. No other driver changes are needed since the chip is accessed through the same generic UCSI/HPI I2C register protocol as the existing cypd4226 support. Link: https://lore.kernel.org/all/20260820145036.2035641-4-akash.kumar@oss.qualcomm.com/ Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Signed-off-by: Akash Kumar <akash.kumar@oss.qualcomm.com>
…ype-C ports On Shikra CQS/CQM platforms, usb-role-switch is handled by PM4125 on the primary Type-C port and Cypress PD controller CYPD6129 on the second Type-C port. On Shikra IQS platform, usb-role-switch is handled by Cypress PD controller CYPD6129 on both Type-C ports. Add the CYPD6129 typec node under i2c3, wire its connector endpoints to the corresponding DWC3 controller ports via remote-endpoint phandles, and switch the associated USB controllers to OTG mode so role switching can take effect. Link: https://lore.kernel.org/all/20260820145036.2035641-4-akash.kumar@oss.qualcomm.com/ Signed-off-by: Akash Kumar <akash.kumar@oss.qualcomm.com>
Add .cyacd2 firmware flashing support to the CCG UCSI driver, and trigger it automatically from probe when the device reports no usable firmware version. Parsing and flashing: - Parse both .cyacd2 and .cyacd firmware text formats (ccg_parse_cyacd2_text, ccg_parse_cyacd_text), auto-detecting the format from file content (ccg_content_is_cyacd2_text), and convert relative/bank-based rows into absolute flash row addresses (ccg_rows_to_absolute, ccg_parse_and_build_rows). - Add HPIv2 register access helpers (ccg_hpi_read16/write16, ccg_i2c_read, ccg_read_u16/u32) and flash primitives (ccg_cmd_write_flash_row, ccg_cmd_read_flash_row, ccg_cmd_validate_fw, ccg_cmd_reset, ccg_cmd_jump_boot_mode, ccg_enter_flashing_robust) needed to write firmware rows and validate/reset the device afterwards. - Detect hybrid flash layout and derive per-bank row ranges (ccg_is_hybrid, ccg_row_size_from_device_mode, remap_rows_to_bank), and add response/async-event draining and wait helpers (ccg_wait_success, ccg_wait_async_event, ccg_drain_responses, ccg_disable_pd_ports) to keep the flashing sequence in sync with the device. - Rework do_flash() to request the firmware image, parse it into absolute rows, enter flashing mode, write and validate the image, and reset the device, with diagnostic logging of parsed rows and readback for bring-up. - Add a "ccg_fw_file" module parameter to override the firmware file name used for flashing, for bring-up/testing. Probe-time update: - When get_fw_info() reports an empty/zero uc->fw_version at probe time, call ccg_fw_update_needed()/ccg_fw_update() to flash the device before creating/registering the UCSI interface, instead of requiring a manual "echo 1 > do_flash" after boot. - Re-run ucsi_ccg_init() and get_fw_info() after a probe-time flash since do_flash() resets the device, so the correct post-flash firmware version is used for the rest of probe. Existing behavior kept: - The "do_flash" sysfs attribute (do_flash_store -> ccg_update_firmware work item) is unchanged and still available to trigger a flash after the driver has loaded.
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ccg firmware update support for cyacd2