The WE# signal must wait 100ns before being asserted LOW after the write protect command transitions to HIGH.
There is no logic to force this in the Flash Interface module.
Solution
- The CPU should send a bus idle mode command after write protect mode commands.
- The bus idle should be repeated 4 times (40Mhz flash clk => 25ns period x 4 = 100ns)
- Bus Idle delays after the Standby and Write Protect modes will need to be added in software
The WE# signal must wait 100ns before being asserted LOW after the write protect command transitions to HIGH.
There is no logic to force this in the Flash Interface module.
Solution