The fifo full/empty signals that are input into the flash control module may not behave properly
In the simulation the next state is chosen based on the state of the signal after the rising edge of the clk, as if they are getting there just beforehand. this means that as soon as the signal is fifo signals it is ready the next state is entered. This may cause the data to be latched early.
The fifo full/empty signals that are input into the flash control module may not behave properly
In the simulation the next state is chosen based on the state of the signal after the rising edge of the clk, as if they are getting there just beforehand. this means that as soon as the signal is fifo signals it is ready the next state is entered. This may cause the data to be latched early.