The Agilex™ 7 Precision Time Protocol System Example Design includes two Ethernet ports with built-in 2-step hardware PTP timestamping capabilities. The integrated Agilex™ 7 Hard Processor System (HPS) operates a PTP software stack that complements the hardware-based timestamping functionality.
The System Example Design (SED) provides the necessary drivers and user applications to support the Linux Network stack, the Linux PTP stack, and network Quality of Service (QoS) through the Linux kernel Traffic Control (TC) system.
This System Example Design supports multiple Ethernet link data rates along with ANLT(Auto-Negotiation and Link Training) feature.
- 10GbE.
- 25GbE.
- 50GbE.
- 100GbE.
The system's primary components include:
- Golden Hardware Reference Design (GHRD)
- Reference HPS software including:
- Arm Trusted Firmware
- U-Boot
- Linux Kernel
- Linux Drivers
- User Space Applications
The block diagram below illustrates the architecture for a 25G design. This architecture is also applicable to other data rates (10GbE, 50GbE, and 100GbE); the only notable change is that the Ethernet subsystem will be replaced with the corresponding IP modules for each data rate.
Directory Structure Used in This Example Design:
|--- agi027fc-si-devkit
| |--- src
| | |--- hw
| | |--- sw
- Family: Agilex™ 7 I-Series
- Quartus Version: 25.3.1
- Development Kit: Agilex&trade 7; I-Series Transceiver-SoC Development Kit (4x F-Tile) (DK-SI-AGI027FC)
- Device Part: AGIB027R31B1E1VB
- Documentation: Agilex™ 7Precision Time Protocol System Example Design
Building the design is easy with the scripts provided in the repo. Clone the repository to get the source files
git clone https://github.com/altera-fpga/agilex7-ed-ptp.git
cd agilex7-ed-ptp
git checkout <tag>Follow the below procedure to build the HW and the Software artifacts.