Allow multi-connector SOURCE/SINK terminals via PDN_P_DES / PDN_N_DES

[cs42]

Motivation

Lab and prototype boards often bring supply in through separate single-pin connectors (banana jacks): one jack for the rail, several for return. FYPA previously required both PDN_P_NET and PDN_N_NET pads on the same annotated footprint, so a two-terminal SOURCE could not be placed on that topology without a kludge (2-pin symbol, wrong injection point, or single-net mode that ignores return copper).

This change lets one logical SOURCE or SINK keep its value on a host part while binding each terminal to pads on other designators — so current injects at the real lab connectors.

Summary

• Add optional PDN_P_DES / PDN_N_DES (and PDNn_*) — comma-separated designator lists for the P/N side. When set, that side uses only those parts’ pads on the named net (host is not auto-included).
• Same semantics in the FYPA editor via p_des / n_des on .fypa directives, plus slim CSV fields in the PDN panel.
• TerminalPin.component_designator and metadata component / pad_label so multi-part terminals stay readable; raw pad stays unlock-safe.
• Docs (user guide + README) and unit tests for resolution, errors, editor round-trip, and unlock seeding.

Example

# on J1 (host)
PDN_ROLE  = SOURCE
PDN_V     = 5V
PDN_P_NET = +5V
PDN_N_NET = GND
PDN_N_DES = J2,J3,J4

Without *_DES, behaviour is unchanged (pads on the host only).

Test plan

• pytest tests/test_annotations.py tests/test_editor_directives.py
• Annotate a P-only jack as SOURCE with PDN_N_DES listing return jacks; confirm N pads/solve use those connectors
• Missing or wrong DES designator → clear error; no pad on net → clear error
• Without *_DES, existing two-terminal sources behave unchanged
• Unlock a multi-DES schematic directive in the editor: DES fields and pin lists seed correctly; Apply keeps remote pads