riscv: Mask mepc[0] and sepc[0]

[whensun]

This PR fixes RISC-V CSR field masking in tlib.

It masks mepc[0] and sepc[0], which are architecturally hardwired to zero.

Related to renode/renode#905
Related to renode/renode#906

[FW-Nagorko]

Thank You for your contribution.

We have been able to verify that the change to mask mepc[0] and sepc[0] is correct, and we will be merging it into the codebase.

We would like to ask you to explain the reasoning behind masking out the menvcfg and menvcfgh registers as the provided reason is too vague.
Specifically why do you think that this register should be zeroed on write?

[whensun]

Hello, thank you for your reply.

I should clarify that my intention wasn't to claim that the entire menvcfg register is zero-on-write. The intention was to enforce the read-only-zero behavior required for fields whose related functionality is not implemented by tlib.

Currently, tlib stores the full written value directly, so writing all ones makes every field read back as one.

The RISC-V Privileged Architecture specification requires the following fields to be read-only zero when their related extensions are not implemented:

• STCE for Sstc
• PBMTE for Svpbmt
• ADUE for Svadu
• CDE for Smcdeleg
• CBZE for Zicboz
• CBCFE and CBIE for Zicbom
• PMM for Smnpm

From my inspection, tlib does not appear to explicitly support these extensions.

Svadu is slightly different because tlib already updates PTE A/D bits automatically, but this behavior is unconditional. I could not find any handling that connects menvcfg.ADUE to the page-table walker. Therefore, ADUE is currently stored and read back, but it does not control the behavior.

I agree that using a zero mask for the entire register is too broad because it also clears unrelated fields such as FIOM.

menvcfgh also needs XLEN-specific handling: it aliases bits 63:32 of menvcfg on RV32, but does not exist on RV64.

I will remove the current menvcfg and menvcfgh changes from this PR and handle them separately with field-specific and XLEN-specific logic.

[whensun]

I have updated the PR.

The menvcfg and menvcfgh changes have been removed and moved to [antmicro/tlib#33], so this PR now only contains the verified mepc[0] and sepc[0] fixes.