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The product goal on Apple Silicon is not only lower OCR latency: OCR must stop occupying the CPU needed by user-facing workloads. Merely registering CoreMLExecutionProvider is not enough because unsupported/dynamic regions can silently execute on MLCPU or fall back to ORT CPU.
Evidence collected on Apple M4 Max
Controlled probes against the current PP-OCRv6 Small ONNX models found:
Dynamic recognition model: CoreML accepts most nodes, but the compute plan reports about 250 operations on MLCPU and only 2 on MLGPU when forced to CPUAndGPU; CPUAndNeuralEngine reports no ANE operations.
Dynamic detection model: the tested compute-unit settings report about 204 operations on MLCPU.
Static recognition shape (example width 1024): the plan reports 278 CoreML operations on MLGPU.
Static detector shape (768×960): the plan reports 229 CoreML operations on MLGPU.
Recognition, 100 warm calls at width 1024: CPU/12 threads = 1.330 s wall and 15.87 process-CPU seconds; static CoreML GPU = 1.069 s wall and 0.80 process-CPU seconds. The important result is about 95% less process CPU, not merely ~1.24× lower wall time.
Static recognition widths 320/1024/2168/3200 were ~1.20–1.50× faster than CPU/12 and used roughly 0.71–0.74 CPU core on average. Random-input argmax matched in the probe; max absolute output difference was <= 3e-5.
Static detector, 20 warm calls: CoreML GPU = 0.216 s versus CPU/12 = 0.856 s (~3.97×), using roughly 0.63 CPU core.
Eight separate static recognition sessions (widths 320..3200) took ~5.97 s to initialize/first-run and peaked around 856 MiB RSS. That is useful spike evidence, but not an acceptable final architecture by itself.
These are microbenchmarks, not yet a full-document product result.
Deliver a qualified Apple Silicon execution path in which both detection and recognition demonstrably execute on CoreML GPU and materially free CPU for foreground application work.
Investigate, in order:
A static detector shape matching the product's bounded detection policy.
Recognition shape specialization using a bounded width set. Widths 320..3200 in steps of 32 are 91 shapes, within Core ML's 128-shape enumerated limit.
Whether one converted Core ML MLProgram with enumerated shapes can replace a bank of ORT sessions. If ORT cannot represent this efficiently, evaluate a small direct-CoreML backend boundary.
Model compilation/cache behavior and FastPrediction specialization.
A minimal bucketing policy only if it passes OCR quality gates; padding/bucketing must not be assumed output-neutral.
Acceptance criteria
Compute-plan evidence shows the intended detection and recognition operations on MLGPU, not predominantly MLCPU or ORT CPU fallback.
Full 15-page reference PDF benchmark reports wall time, process CPU seconds, peak RSS, cold initialization, warm inference, and per-stage timing.
Process CPU consumption drops by at least 80% versus the qualified CPU-fast profile while maintaining useful wall-clock performance.
Golden OCR corpus covers narrow, wide, CJK/Latin mixed, dense forms, rotated/low-quality text, and the reference PDF.
Text, confidence, box geometry, and reading order meet an agreed parity threshold; any precision change is explicit and documented.
Session/model-cache count and peak RSS are bounded; the eight-session/~856 MiB spike is not adopted without a justified budget.
Requested CoreML GPU mode fails loudly or reports degraded execution if the model falls back to MLCPU/CPU.
Packaging, minimum macOS version, architecture support, and cold-cache behavior are documented.
Non-goals
Claiming acceleration from provider registration alone.
Making ANE a requirement: current static probes still show no ANE execution for these models.
Making maximum CPU parallelism the interactive default.
Changing OCR shapes/precision without corpus-level quality validation.
Why
The product goal on Apple Silicon is not only lower OCR latency: OCR must stop occupying the CPU needed by user-facing workloads. Merely registering
CoreMLExecutionProvideris not enough because unsupported/dynamic regions can silently execute on MLCPU or fall back to ORT CPU.Evidence collected on Apple M4 Max
Controlled probes against the current PP-OCRv6 Small ONNX models found:
CPUAndGPU;CPUAndNeuralEnginereports no ANE operations.These are microbenchmarks, not yet a full-document product result.
Upstream facts
MLComputeUnits,RequireStaticInputShapes,SpecializationStrategy, compute-plan profiling, and model caching. Its documentation explicitly warns that dynamic shapes may hurt performance: https://onnxruntime.ai/docs/execution-providers/CoreML-ExecutionProvider.htmlGoal
Deliver a qualified Apple Silicon execution path in which both detection and recognition demonstrably execute on CoreML GPU and materially free CPU for foreground application work.
Investigate, in order:
FastPredictionspecialization.Acceptance criteria
Non-goals