Change the FMC frequency source to HCLK

[Bexin3]

Change the FMC frequency source to HCLK, freeing up PLL2 for other uses. On Portenta, the frequency will be same. On giga it will be higher but still within spec, and timings should get recalculated based on MICROPY_HW_SDRAM_FREQUENCY.

[CLAassistant]

All committers have signed the CLA.

[Bexin3]

Had to do a small change, should be in a final form now though.

[megacct]

Applied this PR to my GIGA and ran its SDRAM intensive workload for 90mins or so. Nil impact. I will continue running with these changes and report any issues

[Bexin3]

Applied this PR to my GIGA and ran its SDRAM intensive workload for 90mins or so. Nil impact. I will continue running with these changes and report any issues

That's great to hear!!
I tried for a bit with video transfer from camera to ram to display and worked well, though didn't test it that long yet.

From my testing I was now able to set PLL2 to any frequency while using ram, which is great as I can now use it to have ADCs run as I want them to. (Though this will be useful for anyone who wants to use PLL2 at different frequencies)

Speed wise with transfers couldn't see any decrease.