Living Weights for GLM-5.3-Flash on NVIDIA GB10 (DGX Spark) CUDA — port request + test hardware offer #566

First — Living Weights looks like the most interesting serving-side work this year. The claims in the launch thread (weight updates gated behind /learn, shard growth with a size cap, persistence across unload and machine moves, cracked catastrophic forgetting) are exactly what personal-model serving needs.

We run GLM-5.3-Flash as our primary pair-served model on two NVIDIA DGX Spark (GB10, sm_121) boxes via TensorFold (stock upstream, currently the 0.6.x Python line at v0.6.6 in Docker — the operator-mandated primary lane since 2026-10-01). LW ships with Nemotron Lightning, you mentioned Qwen3.6-35B-A3B works but is gated for a few days. Questions:

1. GLM-5.3 on the native CUDA server: 1.0.x qualifies GLM-5.3 on two M5 Ultras (Metal). Is GLM-5.3 on GB10 CUDA on the LW/native roadmap? If it needs a port, what does the model gate look like (which measurements must pass)?
2. Living Weights on quantized checkpoints: our serving checkpoint is a 4bpw TR3/EXL3-class mixed-bit GLM quant. Your thread says 4-bit recall "seems really good" — does LW's shard-growth mechanism operate on quantized tensors in place, or does it need a BF16/native-format base? What happens to a mixed-bit checkpoint?
3. Speculative decoding interaction: our GLM lane serves with DFlash2+MTP drafts and verifies reply-equality against plain decoding. Does LW updating live weights break draft/verify equality guarantees, and is draft acceptance re-measured after learned updates?
4. Rollback: is learned state separable from base weights (drop the grown shard / revert to the frozen checkpoint)? Is there a per-/learn-call audit trail (what was written, where)?
5. Cost: what's the per-/learn update cost on CUDA GB10 for a ~30B-class MoE at 4bpw (wall time, memory), and does serving pause during an update?

Happy to give the GLM-on-GB10 native port a real test target: the pair is on my desk, we have py-spy/nccl/pytest harnesses and a round-trip verification lane already built. If a CUDA GLM branch exists behind any door, point me at it.