[akol1]

The CUDA launch audit reports six stale compiler-resource records with NVCC 13.3.73 even when all numerical contracts pass. Re-derive those records from the SM 80, 86, 89, 120 and 121 cubins and document the compiler baseline. Launch dimensions, dynamic shared memory, arithmetic, device bounds and audit tolerances are unchanged.

Updates cover RMS rows, router top-k, lane GEMV and split-K, FP8 prompt16, and the FP4 FP32-output 32-row cluster projection. The inherited register counts remain checked exactly against compiled attributes.

Validation at cb2c74984d4017b780f4e792001e1c3bffd99c59, base 46a08c18608153bfc566703a88acc883bc6140f4:

• Zig 0.17.0 host test test-golden -Dcpu=apple_m1: 208/208 build steps, 2989/2999 tests passed, 10 platform/library skips; golden 309/319 exact with 0 unexpected differences.
• Linux x86_64 build and all five SM cubin compiles with NVCC 13.3.73 (cuda_13.3.r13.3/compiler.38244171_0).
• Actual SM 120 device, RTX PRO 6000 Blackwell: kernel-contract-limits exit 0 and kernel-contract exit 0.
• SUMMARY 12 kernels: 12 pass gates 1-4, 0 fail, 0 known findings; 5 controls: 5 red as planted, 0 missed; 0 limit problems; gates 68864 ms, limits 11 ms.
• Prior exact audit detected six resource problems; updated source detects zero. Planted limit failures remain red as designed.
• SM 80/86/89/121 hardware and Metal execution were not run; the four other architecture records are compiler metadata, not device qualification.

This is a resource-record maintenance change and adds no model, serving path or performance claim.

[cwschroeder]

Narrow source and CPU metadata cross-check at cb2c74984d4017b780f4e792001e1c3bffd99c59 on main 46a08c18: only the six register arrays change; launch dimensions, dynamic shared memory and the other resource fields are unchanged. The host kernel-contract target, full-tree Zig format and whitespace checks pass locally. All four current-head GitHub checks are green.

The QMMF correction also agrees with our existing independent NVCC 13.2.78 artifact from #908: all eight pre-existing QMMF records match on SM120 and SM121, 16 comparisons with zero mismatches. The unchanged main registry fails two of those comparisons, both the 32-row FP4/F32 cluster entry recording 63 instead of 61 registers. The earlier artifact/build receipt and CPU audit records that difference.

This is a reused #908 artifact, not a new compile of this PR's source. It supports that QMMF metadata correction; I have not independently reproduced all six arrays with NVCC 13.3.73 or run a GPU here. Keeping the compiler baseline and the exact audit is appropriate. #908 can inherit this shared-record correction when it rebases.

[akol1]

Thanks for the independent metadata cross-check. The older 32-row FP4/F32 cluster entry is corrected by this PR; #907 and #908 already inherit that correction. At cb2c74984d4017b780f4e792001e1c3bffd99c59, NVCC 13.3.73 compiled all five registered SM images and the complete resource audit exited 0. Actual SM 120 execution reported:

SUMMARY 12 kernels: 12 pass gates 1-4, 0 fail, 0 known findings; 5 controls: 5 red as planted, 0 missed; 0 limit problems; gates 68864 ms, limits 11 ms

The six inherited failures and their correction remain recorded in the description. The other architecture columns are compiler records, not device execution; no audit tolerance or launch dimension was relaxed. No further resource change is needed for the discrepancy identified on #908.

[ashhart]

Thank you, @akol1, for the compiler-derived resource records and the evidence showing their version dependence.

We merged your work for 1.1.0 in be7b71f. The catalog keeps nvcc 13.0's release baseline and ordered later-compiler differences, and audits read compiler identity from each image. Conflicting attribution is refused when no exact device image is available.

Exact resource comparisons, launch limits and planted controls retain their bounds.

NVIDIA GB10/RTX PRO 6000: 55/55 live checks, five controls red, zero stale records with nvcc 13.0/13.2.

Posted by Ash's AI Assistant Synthena