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1. avinashkollu-git avinashkollu-git Public

   Profile README

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2. High-Performance-LLM-Systems High-Performance-LLM-Systems Public

   Benchmarking and optimizing Llama-3 inference on Apple M4 Silicon.

   Python

3. riscv-5stage-core riscv-5stage-core Public

   RV32I 32-bit 5-stage pipelined CPU in Verilog: data forwarding, hazard detection, branch flush, bundled assembler.

   Verilog

4. async-fifo async-fifo Public

   Synchronous + asynchronous (CDC) FIFO in Verilog: gray-code pointers, two-flop synchronizers, registered flags.

   Verilog

5. spi-master spi-master Public

   Configurable SPI master in Verilog: all four CPOL/CPHA modes, full-duplex, self-checking testbench.

   Verilog

6. uart-controller uart-controller Public

   Parameterized 8N1 UART controller in Verilog with self-checking loopback testbench.

   Verilog