This project implements a custom 16-bit single-cycle RISC processor in Verilog. The design demonstrates the fundamental components of a CPU, including instruction fetch, decode, execution, memory access, and write-back.
The processor follows a modular architecture consisting of a datapath, control unit, register file, ALU, and memory modules.
This project was developed as part of a Computer Organization / Digital Design coursework to explore processor design at the hardware level.
- 16-bit instruction width
- Single-cycle execution model
- Custom ALU supporting arithmetic and logic operations
- Register file with general-purpose registers
- Load/store memory interface
- Modular Verilog implementation
- Simulation-ready testbench included
The processor currently supports basic operations such as:
- ADD, SUB
- AND, OR, XOR
- LOAD (from memory to register)
- STORE (from register to memory)
These instructions demonstrate the complete instruction execution pipeline within a single clock cycle.
risc16/
├── alu.v
├── register_file.v
├── program_counter.v
├── instruction_memory.v
├── data_memory.v
├── control_unit.v
├── datapath.v
├── cpu_top.v
└── cpu_tb.v
To simulate the processor, install a Verilog simulator such as Icarus Verilog.
Compile the design:
iverilog -o cpu cpu_tb.v cpu_top.v datapath.v alu.v register_file.v program_counter.v instruction_memory.v data_memory.v control_unit.v
Run the simulation:
vvp cpu
Optional: View signal waveforms using GTKWave.
This project demonstrates:
- Datapath design and signal flow
- Instruction decoding and control logic
- Register-based computation
- Memory access operations
- Hardware modularization in Verilog
- Add branching and jump instructions
- Implement pipelining for performance
- Expand instruction set
- Add assembler for machine code generation
Built as part of a computer architecture project exploring processor design fundamentals.