This is a repository of labs from CSE100: Logic Design With Verilog. Each lab entails programming of an FPGA with certain guidelines including usage of state machines in order to achieve a function on the FPGA board
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This is a repository of labs from CSE100: Logic Design With Verilog. Each lab entails programming of an FPGA with certain guidelines including usage of state machines in order to achieve a function on the FPGA board