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#46/#47/#48 ARCHITECTURE.md: - module map: new rows for jevmlx/timing.py (Ledger, standalone, NOT wired), jevmlx/adapters.py (registry-only, NOT wired), benchmarks/m5.py (runbook), benchmarks/probe.py (slope/adapters probes); engine row gains the #45 anchors (finalize_scalar_evidence, ScalarEvidence/ScalarDecision/Candidate, validate_constraints_for_schema, topological waves + Given header, InternalConstraintViolationError); check_results row gains the v2 gates; leaderboard row documents the no-fallback per-item end-to-end read. - data flow: constraint validation before model work; second-pass waves with the Given: header; new 'scalar decisions (PR #45)' block. - contracts: case-constraints section names validate_constraints_for_schema + InternalConstraintViolationError; field_telemetry gains evidence_source; predictions line adds optional oracle_prediction; timing.json documents the v2 keys (RUN_TIMING_KEYS, BATCHED_TIMING_KEYS); parity gate section documents pre-v2 FAIL + _parity_failed_stages. CHANGELOG.md: six Unreleased entries — W5-B engine restructure (#45), W5b-8 timing ledger (#46, not wired), W6-1 adapters (#42, not wired), M5 runbook (#43), W6-2 probes (#47), results contract v2 (#48) incl. the leaderboard follow-up (per_item_end_to_end_ms only, ValueError otherwise). Code anchors verified against the tree; 655 tests pass, ruff clean.
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Docs-only PR plus the one code follow-up #48's review asked for:
Leaderboard follow-up (code):
_local_rowsreads ONLYper_item_end_to_end_msfor local time-per-case — thelatency_msfallback is deleted (_p50_latency_msremoved). A parallel combo without the key raisesValueErrornaming the folder (check_results already rejects the same shape; there are no pre-v2 folders on main). Tests: v2-fixture render (0.8s @1dp), loud-FAIL test, parity-gate fixture updated.ARCHITECTURE.md (name anchors only, all verified against the tree):
jevmlx/timing.py(W5b-8: timing ledger module (standalone, no engine wiring) #46 Ledger — standalone, explicitly NOT wired),jevmlx/adapters.py(W6-1: LM-head adapters module (standalone) #42 registry — explicitly NOT wired),benchmarks/m5.py(W5b-4: one-command M5 runbook (benchmarks/m5.py) #43 runbook),benchmarks/probe.py(W6-2 prep: probe benchmark (memory slope + adapter parity), m5 --probe steps #47 slope/adapters probes); engine row gains W5-B: shared scalar finalizer, rebuilt dependency second pass, MAP + constraint fixes #45 anchors (finalize_scalar_evidence,ScalarEvidence/ScalarDecision/Candidate,validate_constraints_for_schema, topological waves +Given:header,InternalConstraintViolationError); check_results/leaderboard rows document the v2 gates.evidence_source; predictions line gains optionaloracle_prediction; timing.json documentsRUN_TIMING_KEYS/BATCHED_TIMING_KEYS; parity-gate section documents the pre-v2 FAIL + shared_parity_failed_stages.CHANGELOG.md: six Unreleased entries — W5-B engine restructure (#45), W5b-8 timing ledger (#46, not wired), W6-1 adapters (#42, not wired), M5 runbook (#43), W6-2 probes (#47), results contract v2 (#48).
657 passed, ruff check+format clean.