AMD toolchain initialization

docs/vivado_vitis/xilinx_workflow.md

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+# AMD Vivado + Vitis Workflow for cmod_s7
+
+## Folder Structure
+
+```
+firmware/devices/cmod_s7/
+├── src/
+│   ├── uart.vhd                    ← UART communication (shared)
+│   └── ...
+├── vivado_impl/
+│   ├── cnn_inference/
+│   │   ├── cnn_inference.xpr       ← CNN Vivado project
+│   │   ├── src/
+│   │   │   ├── top_cnn.vhd         ← CNN top entity
+│   │   │   └── ...
+│   │   └── ...
+│   └── tcn_inference/
+│       ├── tcn_inference.xpr       ← TCN Vivado project
+│       ├── src/
+│       │   ├── top_tcn.vhd         ← TCN top entity
+│       │   └── ...
+│       └── ...
+└── vitis_impl/
+    ├── cnn_inference/
+    │   ├── .wsdata/
+    │   ├── src/
+    │   │   ├── top_cnn_hls.cpp     ← CNN HLS kernel
+    │   │   └── ...
+    │   └── ...
+    └── tcn_inference/
+        ├── .wsdata/
+        ├── src/
+        │   ├── top_tcn_hls.cpp     ← TCN HLS kernel
+        │   └── ...
+        └── ...
+```
+## Build Workflow
+
+### CNN Implementation (Vivado + Vitis)
+
+#### Vivado Flow
+1. Open `vivado_impl/cnn_inference/cnn_inference.xpr` in Vivado
+2. Run synthesis, implementation, and generate bitstream
+3. Export the bitstream to `firmware/devices/cmod_s7/vivado_impl/cnn_inference/...`
+
+#### Vitis HLS Flow
+1. Open `vitis_impl/cnn_inference` workspace in Vitis HLS
+2. Synthesize and generate IP for `top_cnn_hls.cpp`
+3. Export RTL to `firmware/devices/cmod_s7/vitis_impl/cnn_inference/...`
+
+### TCN Implementation (Vivado + Vitis)
+
+#### Vivado Flow
+1. Open `vivado_impl/tcn_inference/tcn_inference.xpr` in Vivado
+2. Run synthesis, implementation, and generate bitstream
+3. Export the bitstream to `firmware/devices/cmod_s7/vivado_impl/tcn_inference/...`
+
+#### Vitis HLS Flow
+1. Open `vitis_impl/tcn_inference` workspace in Vitis HLS
+2. Synthesize and generate IP for `top_tcn_hls.cpp`
+3. Export RTL to `firmware/devices/cmod_s7/vitis_impl/tcn_inference/...`
+
+## Shared Components
+
+- **uart.vhd**: UART communication module (used by both CNN and TCN)

firmware/devices/cmod_s7/.gitignore

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+# EDA generated files
+*.jou
+*.log
+*.str
+*.pb
+*.wdb
+*.tr
+*.rpt
+*.pwr
+*.pnr
+*.lock
+*.lck
+*.db
+*.db9
+
+# EDA build folders
+impl/
+syn/
+sim/
+simulation/
+.ipcache/
+
+# HLS build folders
+solution*/
+csim/
+cosim/
+
+# IP Core generated output
+# Keep .ipc config files but ignore generated HDL
+src/ipcore/
+ip/*/
+
+# Bitstreams — KEEP for flashing without synthesis
+# .fs files are committed so team can flash
+# directly without running full synthesis
+# Uncomment the line below to ignore them instead
+# *.fs
+
+# OS / Editor Junk
+.DS_Store
+Thumbs.db
+.vscode/
+*.swp
+
+# Temporary Files
+*.tmp
+*.bak
+
+# User-specific Gowin project settings (like Vivado .xpr.user)
+*.gprj.user
+*.xpr.user
+
+# Bambu generated Verilog output
+src/generated/
+
+# Vivado/Vitis generated files
+*.xsa
+*.sdk
+*.hw
+*.cache
+*.run
+*.export
+*.ip_user_files/
+
+sim/*.vcd
+sim/*.ghw

firmware/devices/cmod_s7/vitis_impl/.gitignore

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+# Ignore build output directory
+/build
+/export
+
+# Ignore object files and dependent files
+.o
+.d
+
+#Ignore logs folder and log files
+/logs
+.log
+
+#Ignore lock files
+.lock
+
+.bin
+.pdi
+.peers.ini
+.repo.yaml
+.vitisWorkspace.json

firmware/devices/cmod_s7/vitis_impl/.theia/settings.json

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+{
+    "clangd.fallbackFlags": [
+        "-IC:\\Xilinx\\Vitis_HLS\\2024.1\\include",
+        "-IC:\\Xilinx\\Vitis_HLS\\2024.1\\include\\etc",
+        "-IC:\\Xilinx\\Vitis_HLS\\2024.1\\include\\ap_sysc",
+        "-IC:\\Xilinx\\Vitis_HLS\\2024.1\\win64\\tools\\auto_cc\\include",
+        "-IC:\\Xilinx\\Vitis_HLS\\2024.1\\win64\\tools\\systemc\\include"
+    ]
+}

firmware/devices/cmod_s7/vitis_impl/.wsdata/clang_dir_map.json

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+{
+  "workspaceRoot": "C:\\GitRepos\\Capstone\\ASL_Gloves_RV1\\firmware\\devices\\cmod_s7\\vitis_impl",
+  "mapping": {}
+}

firmware/devices/cmod_s7/vitis_impl/cnn_inference/.gitignore

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+# Ignore build output directory
+/build
+/export
+
+# Ignore object files and dependent files
+.o
+.d
+
+#Ignore logs folder and log files
+/logs
+.log
+
+#Ignore lock files
+.lock
+
+.bin
+.pdi
+.peers.ini
+.repo.yaml
+.vitisWorkspace.json

firmware/devices/cmod_s7/vitis_impl/cnn_inference/cnn_inference.cfg

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+part=xc7s25csga225-1
+
+[hls]
+flow_target=vivado
+package.output.format=ip_catalog
+package.output.syn=false
+syn.top=cnn_inference

firmware/devices/cmod_s7/vitis_impl/cnn_inference/compile_commands.json

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+[]

firmware/devices/cmod_s7/vitis_impl/cnn_inference/vitis-comp.json

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+{
+  "name": "cnn_inference",
+  "type": "HLS",
+  "configuration": {
+    "componentType": "HLS",
+    "configFiles": [
+      "cnn_inference.cfg"
+    ],
+    "work_dir": "cnn_inference"
+  }
+}

firmware/devices/cmod_s7/vitis_impl/tcn_inference/.gitignore

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+# Ignore build output directory
+/build
+/export
+
+# Ignore object files and dependent files
+.o
+.d
+
+#Ignore logs folder and log files
+/logs
+.log
+
+#Ignore lock files
+.lock
+
+.bin
+.pdi
+.peers.ini
+.repo.yaml
+.vitisWorkspace.json

firmware/devices/cmod_s7/vitis_impl/tcn_inference/compile_commands.json

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+[]

firmware/devices/cmod_s7/vitis_impl/tcn_inference/tcn_inference.cfg

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+part=xc7s25csga225-1
+
+[hls]
+flow_target=vivado
+package.output.format=ip_catalog
+package.output.syn=false
+syn.top=tcn_inference

firmware/devices/cmod_s7/vitis_impl/tcn_inference/vitis-comp.json

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+{
+  "name": "tcn_inference",
+  "type": "HLS",
+  "configuration": {
+    "componentType": "HLS",
+    "configFiles": [
+      "tcn_inference.cfg"
+    ],
+    "work_dir": "tcn_inference"
+  }
+}