A 5-stage pipelined 32-bit MIPS processor implementation.
This project is a pipelined MIPS processor written in Verilog HDL. It uses Harvard architecture with separate instruction and data memories.
- Instruction Fetch (IF) - Fetches instruction from memory using Program Counter
- Instruction Decode (ID) - Decodes instruction, accesses Register File, generates control signals
- Execute (EX) - ALU operations and branch target calculation
- Memory Access (MEM) - Data Memory access for Load/Store operations
- Write Back (WB) - Writes results back to Register File
| Type | Instructions |
|---|---|
| R-Type | ADD, SUB, AND, OR, SLT |
| I-Type | ADDI, LW, SW, BEQ |
- Forwarding Unit - Data forwarding from EX/MEM and MEM/WB stages to ALU inputs
- Hazard Detection Unit - Load-Use hazard detection and stall insertion
- Control Hazard - Pipeline flush on branch taken
PipelineCPU/
├── src/ # RTL Source Files
│ ├── cpu_top.v # Top-level module
│ ├── alu.v # Arithmetic Logic Unit
│ ├── control_unit.v # Control Unit
│ ├── register_file.v # 32x32-bit Register File
│ ├── hazard.v # Hazard Detection & Forwarding
│ ├── instruction_memory.v # Instruction Memory
│ ├── data_memory.v # Data Memory
│ ├── if_id_register.v # IF/ID Pipeline Register
│ ├── id_ex_register.v # ID/EX Pipeline Register
│ ├── ex_mem_register.v # EX/MEM Pipeline Register
│ ├── mem_wb_register.v # MEM/WB Pipeline Register
│ ├── program_counter.v # Program Counter
│ ├── sign_extend.v # Sign Extension Unit
│ ├── shift_left.v # Shift Left Unit
│ ├── adder.v # Adder
│ ├── mux2x1.v # 2-to-1 Multiplexer
│ └── mux3x1.v # 3-to-1 Multiplexer
│
├── tb/ # Testbench Files
│ ├── pipelined_cpu_tb.v # Main CPU testbench
│ ├── alu_tb.v # ALU test
│ ├── control_unit_tb.v # Control Unit test
│ ├── hazard_tb.v # Hazard Unit test
│ ├── regFile_tb.v # Register File test
│ └── ... # Other module tests
│
├── datapath/ # Interactive Datapath Simulator (Web)
│ ├── index.html
│ ├── style.css
│ ├── script.js
│ └── a.svg # Datapath diagram
│
├── program.hex # Test program (hex format)
├── program.txt # Test program (commented)
└── README.md
- Verilog simulator (Icarus Verilog recommended)
- Waveform viewer (GTKWave recommended)
# Clone the repository
git clone https://github.com/tuncaycelikkanat/PipelineCPU.git
cd PipelineCPU
# Compile
iverilog -o cpu_sim src/*.v tb/pipelined_cpu_tb.v
# Simulate
vvp cpu_sim
# View waveform
gtkwave pipelined_cpu.vcdThe project includes an interactive datapath simulator published via GitHub Pages. This simulator:
- Visualizes the pipeline flow of ADD, LW, SW, BEQ instructions
- Provides step-by-step progression
- Supports zoom and pan controls
Demo: https://tuncaycelikkanat.github.io/PipelineCPU/
The program.txt file contains a sample test program:
addi $t0, $zero, 5 # t0 = 5
addi $t1, $zero, 3 # t1 = 3
add $t2, $t0, $t1 # t2 = t0 + t1 (forwarding)
sub $t3, $t1, $t2 # t3 = t1 - t2 (forwarding)
sw $t2, 0($zero) # mem[0] = t2
lw $t3, 0($zero) # t3 = mem[0]
add $t4, $t3, $t2 # t4 = t3 + t2 (load-use hazard)
beq $t4, $t2, label # branch test| Name | GitHub |
|---|---|
| Tuncay Çelikkanat | @tuncaycelikkanat |
| Celil Abdullah Özyürek | @CelilAbdullahOzyurek |
| Furkan Çakı | @cakiFurkan |
| Dila Hazal Bilgin | @dilahazalbilgin |
MIT License