SRAMs with 0 address bits generate invalid Verilog. #11
Description
A 1-word synchronous SRAM is essentially a register, but the generated verilog code contains lines like:
wire [18446744073709551615:0] __mem_da1369;
This is bad.
{{ message }}
A 1-word synchronous SRAM is essentially a register, but the generated verilog code contains lines like:
wire [18446744073709551615:0] __mem_da1369;
This is bad.