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How do you generate the nice logic circuit diagrams.. and do the developers frequent freeside?

Status: Open.

#16 In cdkersey/chdl;

· anderson314159 opened on Dec 2, 2017

verilog generation for wire types

Status: Open.

#13 In cdkersey/chdl;

· ramyadhadidi opened on Jul 25, 2016

Harmonica2 verilog generates "wire release;" which causes error in tool chains

Status: Open.

#12 In cdkersey/chdl;

· ramyadhadidi opened on Jun 21, 2016

SRAMs with 0 address bits generate invalid Verilog.

Status: Open.

#11 In cdkersey/chdl;

· cdkersey opened on Jun 8, 2016

-Wall -Wextra has tons of warnings

Status: Open.

#8 In cdkersey/chdl;

· rcurtin opened on Dec 4, 2014

tri-state merge seems to always increase the number of nodes, sometimes substantially.

Status: Open.

#7 In cdkersey/chdl;

· cdkersey opened on Oct 23, 2014

x = Reg(x); causes segfault in cycdet()

Status: Open.

#4 In cdkersey/chdl;

· cdkersey opened on Oct 14, 2014