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Project Name - openMSP430 with Xilinx AC701 Support

About this Fork

I forked this repository to add dedicated support for the Xilinx AC701 evaluation board.

  • Status: Prom file (.mcs) generation is currently functional and verified.

To-Do List

I am working on the following features to fully support the AC701 workflow:

  1. Flash Programming: Enable support for programming the onboard Flash memory.
  2. MMI Updates: Automate the .mmi (Memory Map Info) file update process.

Quick Start

The build process currently requires a MinGW64 terminal. Follow these steps to generate the bitstream:

  1. Navigate to the synthesis directory:

    cd fpga/xilinx_ac701_board/synthesis/xilinx
  2. Generate the bitstream: Execute the generation script:

    ./0_create_bitstream.sh
  3. Update MMI files (Manual Step): Manually update the .mmi files based on the data in: work/openMSP430_fpga_bram_report.csv

  4. Initialize memory: Run the memory initialization script:

    ./1_initialize_pmem.sh
  5. Generate prom file (.mcs):

    ./2_generate_prom_file.sh

About

The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.

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  • Verilog 70.6%
  • C 10.0%
  • Tcl 5.3%
  • HTML 2.5%
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  • SystemVerilog 2.0%
  • Other 7.5%