Integrate G‑ALP Floating‑Point Compression Scheme

[azimafroozeh]

This PR integrates our G‑ALP floating‑point compression scheme (introduced by Hepkema et al. at DaMoN 2025), enabling high‑throughput compression and decompression of floating‑point numbers on both CPU and NVIDIA GPUs.

Key changes:

G‑ALP integration

• G‑ALP is integrated into the FastLanes file format as separate expressions named EXP_GALP_FLT and EXP_GALP_DBL for both float and double data points.
• Expressions are implemented but not yet inserted into our global expression pool (future work).

G‑ALP benchmarks & tests

• Refactor and integrate the initial CUDA implementation into the FastLanes repo, activated by the CMake option FLS_ENABLE_GALP_TESTING_AND_BENCHMARKING to maintain continuous benchmarking of G‑ALP.

Changes

• The original layout is slightly changed due to a bug in the initial design: 6 bits were reserved for counting exceptions per SIMD lane. In the worst case (double precision) this requires up to 64 exceptions, so we’ve increased the field to 8 bits.
• In the original work, compression was left for future exploration. In this PR, exception parallelization is optimized and runs ~2× faster on average.
• Benchmark result:
  

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Future Work

• Support G‑ALP in the CUDA reader.

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References

• Paper: “G‑ALP: Rethinking Light‑weight Encodings for GPUs,” S. H. Hepkema et al., DaMoN 2025
• Reference implementation: cwida/FastLanesGpu‑Damon2025