baseline arm PR105.0: single-machine dual-GPU (no RPC), PR #110 config reference - #111
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ddvnguyen wants to merge 6 commits into
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baseline arm PR105.0: single-machine dual-GPU (no RPC), PR #110 config reference#111ddvnguyen wants to merge 6 commits into
ddvnguyen wants to merge 6 commits into
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Amended the launch spec (leader review finding): added the flags the 747.0 reference yml sets that were missing from the literal command — |
added 4 commits
September 10, 2026 08:22
Single-machine baseline arm executed on live 2xRTX rig (5060Ti+3060): - build with GGML_CUDA=ON,RPC=ON,FA_ALL_QUANTS=ON,FORCE_CUBLAS=OFF,arch 86;120,CUDA 13.2.2 - boot required deviations from doc spec: -sm row -> layer (CUDA split buffer unsupported), -ts 27,38 -> 38,27 (VRAM balance), -c 296000 -> 262144 (OOM with 38,27), -hf -> -m local path - health 200 PASS, both devices listed - gate 0 spurious PASS, single defer not demonstrated (prompt size/time) - single decode 30.16 t/s FAIL vs 39 bar (22% below) - n=2 concurrent 40.68 agg FAIL vs 49.2-52.6 (17% below) but genuine overlap PASS, no asymmetry - prefill 976 PASS vs 400, determinism PASS, VRAM 15847/11911 marginal vs spec but matches prod - production restored and confirmed healthy on :18081 Assisted-by: muse-spark-1.2-contributor
…67k, decode degrades 50-75% vs shallow bar Co-runs 2 sessions x 10 turns (8000 new + 750 out per turn) on the same single-machine layer topology (-dev CUDA0,CUDA1, ts 38,27, c 262144, np 2) reusing prior build/bin/llama-server. Final prompt_tok 67202/67169 (10.1x growth, 51% of per-slot 131072 ceiling), no truncation/eviction, checkpoint prefix reuse works. Genuine concurrency sustained: 289.3s wall overlap, n_busy_slots_per_decode 1.689, threshold gate defers correctly at >=100k and auto-admits. Per-turn decode falls from 20.38/14.87 (turn1) to 5-6 tok/s mid-depth (mean 10.15/9.87), widening the -22%/-17% single-shot gap vs RPC to ~75% under real multi-turn accumulation. Prefill ~595-731 tok/s. Production restored twice (15847/11911 MiB, :18081 health 200). Assisted-by: muse-spark-1.2-contributor
…d (2.44/33.52 t/s cells)
…n-process best 42.98, RPC 27,38 optimal (47.09)
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Baseline arm derived from the PR #110 verified config with the topology reduced to a single machine: both GPUs in one
llama-serverprocess, RPC peer removed. Binary and all other knobs identical to PR #110 — only the launch topology changes.Commits
docs/arms/pr105-single-machine-baseline.md): config-deltas table vs PR feat(server): --parallel-ctx-threshold admission gate + UM prefetch net (hydra#747 baseline) #110, canonical launch line, hypothesis, verification plan with pass criteria, test plan.Config deltas vs PR #110 rig
rpc-serveron CUDA1 (3060)-dev CUDA0,CUDA1-sm row -ts 27,38, threshold 100000,-np 2, K q8_0 / V q5_1,--spec-type draft-mtp, UM on, FA-all-quants buildGGML_RPC=ONstays in the build so one binary serves this arm and the upcoming PR103.0 (GDN cache-cpy fusion) / PR104.x (mixed-quant row sharding) arms.Hypothesis
Prior single-machine trial showed dropping RPC does not materially change decode — the wall is the 3060's bandwidth x VRAM-forced share, not RPC overhead. Expected: within-noise parity with the PR #110 bar. Value of the arm:
Verification plan (arm102 bars as reference)
Primary cell only for first pass; secondary cell (kv_unified on / V q4_1, bar 38.4) once primary passes.
Test plan
GGML_CUDA_FORCE_CUBLASoff/health200, both devices in device logAI usage disclosure: YES — arm spec and PR body drafted by AI (opencode) from the PR #110 verified config and local flag verification (
common/arg.cpp,docs/speculative.md);-c 296000(per-slot 148000 x 2) is carried from the arm102 record and flagged in the doc for confirmation against the arm102 yml before first boot. Repo owner to verify launch line on the rig before running.