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[rtl] Add AXI4-Lite register block - #3

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drewbabel merged 4 commits into
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axil-csr
Jul 31, 2026
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[rtl] Add AXI4-Lite register block#3
drewbabel merged 4 commits into
mainfrom
axil-csr

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Adds an AXI4-Lite peripheral holding four control registers with byte-lane write strobes, a self-checking testbench, and a SymbiYosys proof against the ZipCPU faxil_slave property set.

Bus compliance is judged by the third-party property set rather than by properties written here. Since those properties watch only the handshakes, a shadow copy of one solver-chosen register adds the separate claim that a read returns what the write strobes put there. Both gates were mutation tested, ten of ten caught in sim and ten of ten in formal.

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drewbabel merged commit b13178c into main Jul 31, 2026
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drewbabel deleted the axil-csr branch July 31, 2026 01:01
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