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[rtl] Size the register file from ADDR_WIDTH - #5

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drewbabel merged 2 commits into
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axil-widths
Jul 31, 2026
Merged

[rtl] Size the register file from ADDR_WIDTH#5
drewbabel merged 2 commits into
mainfrom
axil-widths

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@drewbabel drewbabel commented Jul 31, 2026

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Derives NumRegs from the address width so the register array is exactly as deep as the write and read index can address. It was hardcoded at four while IdxWidth followed ADDR_WIDTH, so any instantiation with a wider address space silently dropped writes above index three.

Adds prove and cover tasks at ADDR_WIDTH 5 with DATA_WIDTH 64, and at ADDR_WIDTH 6 with DATA_WIDTH 32, so the block is proved at both AXI4-Lite data widths and at a register file larger than the default. The ADDR_WIDTH 6 configuration failed before this fix and passes after, which is what caught the bug.

@drewbabel drewbabel changed the title [formal] Prove the 64-bit configuration [rtl] Size the register file from ADDR_WIDTH Jul 31, 2026
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drewbabel merged commit 65b1f46 into main Jul 31, 2026
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drewbabel deleted the axil-widths branch July 31, 2026 01:59
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