[rtl] Add the 2x2 AXI-Stream switch - #7
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Adds a 2x2 AXI-Stream switch that routes each packet on its tdest field, arbitrating per packet so beats from two sources never interleave on one output. Each output owns a round-robin arbiter and a skid buffer, and the input side asserts tready only when its granted output will take the beat that cycle. The testbench runs both sources against random destinations, forced contention on a single output, and random backpressure, checking per-flow data and tlast order, packet atomicity at each output, and output handshake stability.
The proof covers AXI-Stream compliance on all four ports, routing and mux correctness, packet atomicity, symbolic end-to-end beat delivery over a solver-chosen source, destination, and beat index, and a bounded wait per output under fair source and sink assumptions. Child instances are read as plain RTL so their own assume statements cannot constrain the switch and rig the result. Every formal task now gets its own CI job.