AI-assisted chip design in the browser, for engineers who are not Verilog experts.
Describe what a chip should do in plain words, give examples of how it should behave, and Wafersmith turns them into a specification and tests. An AI agent writes the Verilog until every example passes. The design then goes from RTL to a sign-off-checked layout (GDS) on the IHP SG13G2 130 nm open PDK, and the results are explained in plain language. Engineers who do write Verilog work on the same project in a full code editor.
Wafersmith is an initiative of DigitalTwin Technology GmbH, which started the project and leads its development.
· Licensed under Apache-2.0 · Changelog
| Describe | Say what the design does; an assistant drafts the connections, settings and examples and asks about anything left open. |
| Examples are the tests | Each example compiles into a testbench. A change, by a person or the AI, is only accepted when every example passes. "What actually happened" shows the design's behaviour cycle by cycle against the example. |
| Blocks | Build the chip from your design, imported IP and adapters on a canvas; every connection is checked, and the assistant reviews what they mean. |
| Health | Builds the layout and reports in plain words whether it works (also on the synthesised gates), is fast enough, can be manufactured, and its size and power. |
| Code | Real-time co-editing, a Verilog language server, browser simulation with waveforms, and Git history for every project. |
| RTL → GDS | LibreLane in containers, a WebGPU layout viewer with DRC markers, timing and area reports, gate-level simulation. |
| AI agent | Proposes changes that can only be merged when the simulation gate passes, with an evidence log. |
| IP registry | Publish blocks, import them pinned to a commit, with licence compatibility checks. |
Works today, checked end to end in the release rehearsal:
- Small designs (counters, a UART, a FIFO, a debouncer and the like) from the start page to a layout that passes DRC, LVS and timing on IHP SG13G2, without typing Verilog or testbench code.
- Examples as tests, coverage of every branch, planted mistakes, and searches that find the examples still missing. A failing example can be explained value by value ("why is it this value?", "why wasn't it the expected one?") and often repaired by a small fix, all without AI.
- Two people editing the same project live; Git history for everything.
- Running it all on one machine, from a clean clone, by following Getting started.
Not yet, or only partly:
- Larger designs. Everything has been tested at starter size (up to a few hundred cells). The simulator covers the synthesisable Verilog these designs use plus functions, tasks and generate blocks, not all of Verilog or SystemVerilog.
- What only an expert can sign off: I/O pads and pin placement, manufacturing test (scan), behaviour at power-up, timing with real gate delays in simulation, analog parts, and the final go/no-go for a real chip run. Health says so on every project.
- AI features need a key and cost money. Describing a change in words, the assistant and the agent use Claude (or OpenRouter) and count against a daily budget; without a key they are off and everything else works. Their quality is measured by the design evals.
- Tested on one setup: Linux on aarch64, with Docker. Other platforms should work but have not been checked.
You need Rust, Node 22 with pnpm, and Docker. Full instructions, including the WebAssembly toolchain, the PDK and the development accounts, are in docs/getting-started.md.
./scripts/fetch-verible.sh && ./scripts/fetch-pdk.shdocker compose -f deploy/compose/docker-compose.yml up -dcp .env.example .env && cargo run -p wafer-apipnpm install && pnpm dev:webThen open http://localhost:5173, sign in, and follow Your first chip.
| Getting started | Running everything locally, development accounts, tests |
| Your first chip | Step by step with screenshots: a design from the start page to a checked layout in ten minutes |
| User guide | Design view, Blocks, examples, Health, code editing, runs, agent, IP registry |
| Architecture | Components, data flow, storage, trust boundaries, design decisions |
| API reference | HTTP and WebSocket endpoints, roles, errors |
| Configuration | Every environment variable |
| Development | Workflow, conventions, CI, migrations, how to add a feature |
| Design evals | Task set, checks, pass rate and cost per task for the assistant and agent |
| Pilot deployment | One-host HTTPS deployment, backups and restore |
| Security review | What was reviewed, fixed and accepted before the pilot |
| Phase 0 gate | The first end-to-end milestone |
| Release rehearsal | Three starters to a clean layout, timed, before 0.1.0 |
Contributions follow CONTRIBUTING.md; report vulnerabilities as described in SECURITY.md.
crates/
wafer-api/ HTTP API and workers (binary: wafersmith-api)
wafer-git/ per-project bare Git repositories (libgit2)
wafer-jobs/ flow-run backends: LibreLane in Docker, metrics and report parsing
wafer-sim/ event-driven Verilog simulator, checked against Icarus Verilog
wafer-sim-wasm/ the simulator for the browser (WebAssembly)
wafer-gds/ GDSII reader for the layout viewer
wafer-gds-wasm/ the GDS reader for the browser (WebAssembly)
apps/web/ React + TypeScript web app (Vite, Monaco)
deploy/compose/ local development services (Postgres, Rauthy)
deploy/pilot/ pilot deployment (Caddy, API, Postgres, Rauthy, backups)
docs/ documentation
scripts/ toolchain and PDK setup, code generation
Wafersmith was initiated by DigitalTwin Technology GmbH. It builds on open-source work including LibreLane, the IHP SG13G2 open PDK, Verible, Rauthy, Yjs/yrs, Monaco and Icarus Verilog. See NOTICE.
Copyright 2026 DigitalTwin Technology GmbH and the Wafersmith contributors. Licensed under the Apache License, Version 2.0.