An independent out-of-tree Linux kernel module (DRM/KMS) for NVIDIA Fermi-architecture GPUs, specifically the GeForce GT 430 (GF108 chip).
Full support for NVIDIA Fermi cards on modern Linux kernels (6.x+), fixing key power-management (reclocking) gaps that remain unaddressed in the existing nouveau driver for this generation of hardware.
- Isolation from nouveau. The driver is written as a standalone module built on the standard Linux Kernel DRM API, not as a fork of the nouveau codebase.
- Reference-only approach. The nouveau and envytools codebases are used strictly as a specification and reference for MMIO registers, VBIOS table structures, and the I2C bus algorithms. No code is copied directly.
- Portability. The build is based on DKMS, ensuring the driver is portable across distributions (Arch, Ubuntu, Mint, Fedora).
| Parameter | Value |
|---|---|
| Card | GeForce GT 430 |
| Chip | GF108 (Fermi) |
| Vendor ID | 0x10de |
| Device ID | 0x0de1 |
nv_fermi_drv.h-- shared macros, register defines, data structures (nv_fermi_priv,nv_dcb_header), function prototypes.core.c-- module init/exit, PCI driver registration, probe/remove.vbios.c-- VBIOS parsing: expansion ROM read, BIT table, DCB table.i2c.c-- GPIO/I2C engine (in progress).Makefile-- Kbuild build file, linkscore.o vbios.o i2c.ointonv_fermi_drv.ko.
The project is currently in Phase 3 (see the table below).
- Repository structure and Makefile for building on Arch Linux.
- PCI ID registration for the device (10de:0de1).
- Module load/unload functions with dmesg logging.
- Confirmed device takeover from the stock kernel driver.
- Device activation via
pci_enable_device(). - Region reservation via
pci_request_regions(). - Mapping of BAR0 (registers) and BAR1 (video memory) via
pci_ioremap_bar(). - Basic register read/write macros (
ioread32/iowrite32). - Reading and decoding
NV_PMC_BOOT_0, confirming the chipset ID (0xC1 = GF108).
VBIOS parsing (complete, verified on real hardware):
- VBIOS location and read via
pci_map_rom(), with option ROM signature validation. - BIT (BIOS Information Table) parser: signature search, header parsing, enumeration of all subsystem tokens, header checksum check.
- DCB (Device Configuration Table) location: tries the BIT token
ifirst, falls back to the legacy pointer at 0x36, and picks whichever candidate produces a plausible DCB header (on this hardware, the BITipointer turned out to be wrong -- the legacy pointer is the one that works). - DCB header parsing (version, header size, entry count and size), plus DCB entry table hex-dump.
- I2C table offset confirmed at DCB header+0x04 (verified against real table content, not just header shape).
- GPIO table offset confirmed at DCB header+0x0a (verified against real table content -- the header+0x06 field, which some references suggest, turned out to point at executable code on this VBIOS, not a table).
Not yet done (this is the part still open):
- Decoding the individual I2C and GPIO table entries (bitfields for line/function/address).
- I2C/SMBus engine initialization in
i2c.c-- currently a stub that logs and returns.
Extracting PSTATE performance profiles, writing a PWM voltage-control driver, PLL clock control code, a basic in-kernel power-management daemon.
DRM/KMS subsystem integration for display init and video output management, GEM/TTM memory manager for framebuffer allocation, a minimal userspace Mesa Gallium3D state tracker.
Requires the headers for your currently running kernel to be installed.
git clone https://github.com/eco1kd/NovaFermi.git
cd nv-fermi-drv
makesudo make loadIf the card is already claimed by the stock driver (nouveau), unbind it first:
echo "0000:XX:00.0" | sudo tee /sys/bus/pci/drivers/nouveau/unbind
echo "0000:XX:00.0" | sudo tee /sys/bus/pci/drivers/nv_fermi_drv/bindFind the device's bus address with lspci -nn | grep 10de.
sudo make logor directly:
sudo dmesg -w | grep nv_fermi_drvsudo make unloadThis project is at an early development stage and works with undocumented NVIDIA hardware via direct MMIO and VBIOS access. The current phases (1-3) are limited to read operations and do not change the card's power or clock state. Starting with Phase 4, the driver will write to registers controlling voltage and frequency -- use at that stage will come with additional warnings and safety guards.
GPL-2.0