feat(vm): 8 opcode handler modules (4)

[haeter525]

Summary

Fills in the handler modules with the following type of instructions:

• arithmetic
• array
• branch
• compare
• field
• throw
• type_check
• type_convert

So the VM can execute every non-stub-dependent opcode end-to-end.

Depends on #4 (Emulator Foundation) which depends on #5 (parser). Base of this PR is pr-b/vm-scaffold; once #4 and #5 merge, the base auto-updates to main and the diff shrinks to handler-only.

Scope

Area	Change
src/dextrace/vm/handlers/	8 new handler modules (arithmetic, array, branch, compare, field, throw, type_check, type_conv)
src/dextrace/vm/engine.py	Add handler imports + register() calls
tests/vm/	test_{arithmetic,wide_arithmetic,handlers,type_check,throw_signal,trace,call_return}.py — handler unit tests + engine integration
tests/test_vm_run_*.py	arrays, fibonacci, inheritance, instance_fields, interface_dispatch, long_arithmetic, packed_switch, try_catch, try_catch_with_fields — end-to-end execution tests
tools/gen_*_fixture.py	8 new fixture generators (auto-run by tests/conftest.py at session start; the generated .dex files are gitignored)

One-line verification

pytest tests/vm/test_arithmetic.py tests/vm/test_wide_arithmetic.py -q

Full suite:

pytest -q   # 314 passed

[sidra-asa]

The PR is structurally cleaner after rebasing onto main, and the existing test suite passes. However, several VM semantics still need tightening before merge.

1. Set pending_result_pc for filled-new-array

File: src/dextrace/vm/handlers/array.py

filled-new-array produces a pending result that must be consumed by the immediately following move-result-object. It currently sets pending_result but does not set pending_result_pc, so the engine cannot enforce the pending-result consumer invariant.

Suggested fix

state.pending_result = handle
state.pending_result_is_wide = False
state.pending_result_pc = insn.uoff + insn.size_units

Also clear pending_result_pc in all move-result* handlers after consumption.

2. Implement Java/Dalvik float-to-integral narrowing semantics

File: src/dextrace/vm/handlers/type_conv.py

float-to-int, double-to-int, float-to-long, and double-to-long currently call Python int(). This raises on NaN / Infinity, while Java/Dalvik conversions should produce deterministic narrowed values.

Suggested fix

Add conversion helpers that handle NaN, +Infinity, -Infinity, and overflow boundaries, then replace direct int(f) / int(d) calls with those helpers.

3. Store ushr-int* results as signed 32-bit register values

File: src/dextrace/vm/handlers/arithmetic.py

ushr-int* currently writes raw unsigned Python integers. For example, -1 >>> 0 becomes 4294967295, but the Dalvik register should hold the signed 32-bit value -1.

Suggested fix

Wrap all ushr-int* results with i32(...):

state.registers.set(dest, i32(u32(a) >> (b & 0x1F)))

Apply the same change to /2addr and /lit8.

4. Add width-specific array and field handlers for byte/short/char/boolean

Files:

• src/dextrace/vm/handlers/array.py
• src/dextrace/vm/handlers/field.py

The typed variants currently share generic _aget/_aput and _iget/_iput logic. This misses Dalvik width semantics: byte and short should sign-extend, char should zero-extend, and boolean should normalize to 0/1.

Suggested fix

Add width helpers such as _i8, _i16, _u16, and _bool, then register typed closures separately for array and field handlers. Add regression tests like:

255 -> aput-byte -> aget-byte == -1
255 -> iput-byte -> iget-byte == -1