Name		Name	Last commit message	Last commit date
M_RISC_V		M_RISC_V
innovus		innovus
report		report
sim		sim
src		src
syn		syn
.DS_Store		.DS_Store
README.md		README.md

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ISA_2020_Group_09_Lab_3

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Favero Simone s270686 Micelli Federico s270456 Spanna Francesca s278040

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Integrated Systems Architecture - RISC V processor implementation

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