Feat/init pipeline compiler#2
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LukeAnger1 wants to merge 2 commits into
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This is the initial pipeline. I would want to add in code with as few changes as possible.
This is the summary:
Removed the test_emit because this was not working at the initial setup.
I opened this issue to ask the next steps #1 .
I would still like to port over the rest of our tests. Depending on how this repo is organized, we can use
iverilogto simulate the compiled code and test the actual Verilog/System Verilog code.I also have code that would be helpful to port over for generating macros and mems for this. Just depends on how much into depth you want to go.