Overview: This project implements a simple general-purpose processor using VHDL and Quartus for FPGA implementation. The design focuses on developing the major components of a processing unit and integrating them to perform arithmetic, logical, and decision-based operations. The project includes two latches, a finite state machine (FSM), a 4-to-16 decoder, and multiple ALU configurations.
Latch1 and Latch2: Two latches are used to temporarily store the 8-bit input values A and B. The stored values are provided to the ALU for processing.
Finite State Machine:
The FSM cycles through nine states, from s0 to s8, before returning to s0. It outputs the current state as well as one digit of the student ID. The current state is used to control the operation performed by the ALU.
4-to-16 Decoder: The decoder converts the FSM's current state into a 16-bit microcode signal. Each microcode corresponds to a specific ALU operation. The decoder was constructed using two 3-to-8 decoders, AND gates, and a NOT gate.
ALU_1: The first ALU implements nine arithmetic and Boolean operations using two 8-bit inputs, A and B, and the 16-bit microcode generated by the decoder.
Operations include:
- Addition
- Subtraction
- Passing A
- AND
- NAND
- XOR
- NOR
ALU_2: ALU_2 maintains the operations from ALU_1 while modifying one function. Function 5 was changed to perform the operation:
B - 5
This required implementing the operation using binary arithmetic and two's complement concepts.
ALU_3:
ALU_3 uses the student ID output from the FSM directly as an input to the ALU. Instead of displaying hexadecimal operation results, the FPGA displays either y or n.
The implemented operation determines whether each student ID digit is even or odd:
- Even →
y - Odd →
n
- VHDL
- Quartus
- FPGA
- Digital logic design
- Finite state machines
- ALU design
- Decoders
- Latches
- Microcode
- Binary arithmetic
The ALU uses two 8-bit inputs, A and B. The operation is selected using a 16-bit microcode signal from the decoder.
For ALU_1 and ALU_2, the result is represented using two 4-bit outputs that together form the complete 8-bit result. ALU_3 instead produces a 4-bit output used to display y or n on the FPGA's seven-segment display.
- Data storage using latches
- Sequential control using an FSM
- Instruction selection using microcode
- Decoding using a 4-to-16 decoder
- Arithmetic and Boolean operations using an ALU
- FPGA implementation using VHDL and Quartus
Report: The complete project report is included in this repository and contains the VHDL implementations, block diagrams, state tables, truth tables, ALU configurations, and waveform results.