This repository contains Verilog modules, simulations, and lab assignments developed for the Digital System Design course. It includes implementations of fundamental digital circuits, testbenches, and practical exercises used throughout laboratory sessions.
Laboratory schedule covered in this repository:
- Lab 1 – Module Instantiation
- Lab 2 – BCD Counter
- Lab 3 – Switch Debouncer
- Lab 4 – Serial Transmitter/Receiver 1
- Lab 5 – Serial Transmitter/Receiver 2
- Lab 6 – Finite State Machine
- Lab 7 – Bidirectional Data Transfer