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VHDL
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17 Commits
17 Commits
AdderAndSubtract
AdderAndSubtract
CoderSpecial
CoderSpecial
Counter18bits
Counter18bits
CounterHex4bits
CounterHex4bits
CounterHexResetLoadEnable
CounterHexResetLoadEnable
Dec24
Dec24
Decoder24NEW
Decoder24NEW
DecoderPriorityNEW
DecoderPriorityNEW
FlipFlopD
FlipFlopD
Happy Birthday
Happy Birthday
Hex0
Hex0
MUX21NEW
MUX21NEW
Mux21
Mux21
Mux41
Mux41
OR2GateNEW
OR2GateNEW
Parte2
Parte2
Register
Register
SEGMENT7NEW
SEGMENT7NEW
XNOR
XNOR
XOR
XOR
XOR3VAR
XOR3VAR
DE2_115.qsf
DE2_115.qsf
README.md
README.md
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VHDL
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Language for FPGA DE2-115
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