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secded_ram – SECDED RAM in Verilog

secded_ram is a Verilog-based RAM module with Single Error Correct, Double Error Detect (SECDED) capabilities.

It supports 8-bit and 16-bit word widths, is FPGA-ready, and can be integrated into ASIC designs.

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Features

• Configurable data width (8-bit / 16-bit)
• SECDED (Hamming) ECC for single-bit correction and double-bit detection
• CPU-style interface via FPGA wrapper
• Simulation-ready with testbenches and error injection
• Full documentation for ECC algorithm and RAM layout

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Quick Links

• Getting Started
• ECC Algorithm
• Memory Map
• Simulation
• FPGA Integration
• Error Injection & Testing
• Release Notes
• FAQ & Tips