Register Optimization Design for mexce

[imakris]

…MM4/XMM5)

Phase 1 - x87 backend GPR address caching:

• Add gpr_cache struct to track addresses in R10, R11, and RAX
• Add analyze_variable_frequency() to identify hot variables
• Add preload_address_caches() to load hot addresses into R10/R11 at start
• Modify compile_elist to check R10/R11 cache before falling back to RAX
• Update asmd_optimizer to use new cache infrastructure
• Saves ~9 bytes per access for cached variables (3-byte load vs 12-byte mov+load)

Phase 2 - SSE2 backend XMM value caching:

• Add xmm_value_cache struct to cache values in XMM4/XMM5
• Modify compile_elist_sse2 to check XMM cache before loading from memory
• Cache hot variables when stack depth <= 3 to avoid register conflicts
• Invalidate XMM cache after libm function calls (XMM4/5 may be clobbered)
• Saves memory load latency (1 cycle movsd reg-reg vs 4-7 cycle memory load)

Both optimizations maintain bit-identical results - all 44229 benchmark expressions pass with unchanged ULP precision statistics.